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  1. #1
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    SISO design using behaviourial modeling in verilog

    I have written verilog code for 4 bit Serial in serial out.

    module siso(
    input clk,reset,in,
    output reg [3:0] out);
    reg [3:0]temp;
    always @ (posedge clk)
    begin
    if (reset)
    begin
    out <= 0;
    temp <= 0;
    end
    else
    begin
    temp[0] <= in;
    temp <= temp << 1;

    out <= temp[3];
    end
    end
    endmodule

    output is coming 0000 and even in temp input is not loading. I am not understanding why its happening like this.

    if i swap the statements
    temp[0] <= in;
    temp <= temp << 1;
    as
    temp <= temp << 1;
    temp[0] <= in;
    output is coming.
    PLZ tell me why its not working with the previous structure.

    Thanks in advance

    •   Alt19th September 2013, 08:05

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  2. #2
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    Re: SISO design using behaviourial modeling in verilog

    Code:
    temp <= temp << 1;
    Shifts a 0 into the LSB.
    You should code a shift register like this...
    Code:
    temp <= {temp[2:0], in};
    Which does the exact same thing as this...
    Code:
    temp[0] <= in;
    temp[1] <= temp[0];
    temp[2] <= temp[1];
    temp[3] <= temp[2];
    Which will work regardless of the ordering of the assignments.

    Regards



    •   Alt19th September 2013, 08:34

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  3. #3
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    Re: SISO design using behaviourial modeling in verilog

    Quote Originally Posted by ads-ee View Post
    Code:
    temp <= temp << 1;
    Shifts a 0 into the LSB.
    You should code a shift register like this...
    Code:
    temp <= {temp[2:0], in};
    Which does the exact same thing as this...
    Code:
    temp[0] <= in;
    temp[1] <= temp[0];
    temp[2] <= temp[1];
    temp[3] <= temp[2];
    Which will work regardless of the ordering of the assignments.

    Regards
    thanks for the reply but i have checked with the same after swapping both the statement it is not giving the output.



    •   Alt19th September 2013, 09:37

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  4. #4
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    Re: SISO design using behaviourial modeling in verilog

    Quote Originally Posted by dkvlsi View Post
    thanks for the reply but i have checked with the same after swapping both the statement it is not giving the output.
    What statements are referring to? Post the code.



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    Re: SISO design using behaviourial modeling in verilog

    ads-ee is correct....
    just check this code.....

    always @ (posedge clk)
    begin
    if (reset)
    begin
    out <= 0;
    temp <= 0;
    in <= 1'b1; //just for testing make it "1"...
    end
    else
    begin
    //$display(" value of in %d",in);
    //temp[0] <= in;
    //$display(" value of temp[0] %d",temp[0]);
    //temp <= (temp << 1);
    temp <= {temp[2:0], in};
    $display("value of temp %b",temp);
    out <= temp[0];
    end
    end

    it's working very fine.....



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    Re: SISO design using behaviourial modeling in verilog

    I think to reflect SISO operation...

    module siso(
    input clk,reset,in,
    output reg out );
    reg [3:0]temp;


    always @ (posedge clk)
    begin
    if (reset)
    begin
    out <= 0;
    temp <= 0;
    //in <= 1'b1; //just for testing make it "1"...
    end
    else
    begin
    temp <= {temp[2:0], in};
    //$display("value of temp %b",temp);
    out <= temp[3];
    end
    end
    endmodule



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