Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Assura LVS question - top cell pins

Status
Not open for further replies.
E

eeStud

Member level 1
Joined
Feb 17, 2011
Messages
37
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,527
Hi,
When i am running Assura LVS i am getting mismatch between layout & schematics regarding the top cell pins (the pins are at the beggining of the top cell SUBSET definition in the cdl file).

How can i prevent this mismatch?

Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top