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Standard Cell Libraries in ASIC flow

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mehboobali

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Why the Standard cell Libraries (.lib) is used in ASIC flow. What happens if we dont use it....
Other than providing .lib in ASIC flow are there any other things which we can give input rather than .lib.?
The .lib process goes this way
Layout-->GDSII-->CDL(netlist)-->Spice extraction-->.lib-->db-->views

Why .lib is used in ASIC flow....??
 

Liberty file contains a simplest timing view (simple versus spice), functionality description, power information for the std cell and any macros you need.
I will say all synthesis tools must have this one to be able to transform a RTL code into netlist.
And also the liberty must contains at least a flop and a AND gate.
 

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