kmegamind
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I am trying to use the barrel shifter provider by the design ware library
so i am using this code which i copied from the examples coming with the library
but i get the following warning during compilation
which makes my design have zero area as if the design ware unit was not included
what should i do ?
so i am using this code which i copied from the examples coming with the library
Code:
library IEEE,DWARE,DWARE;
use IEEE.std_logic_1164.all;
use DWARE.DWpackages.all;
use DWARE.DW_foundation_comp.all;
entity DW01_bsh_inst is
generic (inst_A_width : POSITIVE := 8;
inst_SH_width : POSITIVE := 3);
port (inst_A : in std_logic_vector(inst_A_width-1 downto 0);
inst_SH : in std_logic_vector(inst_SH_width-1 downto 0);
B_inst : out std_logic_vector(inst_A_width-1 downto 0));
end DW01_bsh_inst;
architecture inst of DW01_bsh_inst is
begin
-- Instance of DW01_bsh
U1 : DW01_bsh
generic map ( A_width => inst_A_width, SH_width => inst_SH_width )
port map ( A => inst_A, SH => inst_SH, B => B_inst );
end inst;
-- pragma translate_off
configuration DW01_bsh_inst_cfg_inst of DW01_bsh_inst is
for inst
end for; -- inst
end DW01_bsh_inst_cfg_inst;
-- pragma translate_onbut i get the following warning during compilation
Code:
Warning: Design 'DW01_bsh_inst' has '1' unresolved references. For more detailed information, use the "link" command. (UID-341)
Alib files are up-to-date.
Warning: DesignWare synthetic library dw_foundation.sldb is added to the synthetic_library in the current command. (UISN-40)
Information: Sequential output inversion is enabled. SVF file must be used for formal verification. (OPT-1208)which makes my design have zero area as if the design ware unit was not included
what should i do ?
