Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

CMOS comparator design

Status
Not open for further replies.
A

analogckt

Newbie level 4
Joined
Aug 14, 2013
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
37
Hello

I am trying to design a CMOS comparator. The comparator's input range is 0.6V and out puts should swing at full supply range of 1.8V. It should be able to operate at very high speeds (500MHz or more). I am not sure how to start my design or what architecture to choose. I have seen some structures on Allens book. But again since I am a newbie in CMOS design this is complicated. Any help is appreciated

Thanks
Ackt
 

If by "operate" you mean full rail-rail swing and 500MHz
toggle rate with a usefully small input overdrive, that's
going to want some exotic technology. Says to me that
your GBW product ought to be about 50GHz (figuring
you'd like less than 1% input gain error so A=100 at
speed).

Now the more input error you can tolerate, the lower
the GBW can be.

I think if this is achievable at all, it will be a cascade
of high bandwidth, low gain stages and perhaps a
clocked (sampling) regenerative design with some power
gating away from the sampling edge. Otherwise you'll
be driving things real hard and hot.

Now ask yourself this - is 500MHz a sampling clock rate,
or the bandwidth of the input signal that you must
compare with some (and how much?) accuracy?
 
dick_freebird said:
If by "operate" you mean full rail-rail swing and 500MHz
toggle rate with a usefully small input overdrive, that's
going to want some exotic technology. Says to me that
your GBW product ought to be about 50GHz (figuring
you'd like less than 1% input gain error so A=100 at
speed).

Now the more input error you can tolerate, the lower
the GBW can be.

I think if this is achievable at all, it will be a cascade
of high bandwidth, low gain stages and perhaps a
clocked (sampling) regenerative design with some power
gating away from the sampling edge. Otherwise you'll
be driving things real hard and hot.

Now ask yourself this - is 500MHz a sampling clock rate,
or the bandwidth of the input signal that you must
compare with some (and how much?) accuracy?
Click to expand...

Hi dick_freebird

Thanks for the reply.
How should I determine the bandwidth requirement of the comparator. I am really a newbie here. The input signal swings at 500MHz from 0.5 to 1.5V (Thus 1V swing). I need the output to swing from 0V to 1.8V at 500MHz. I do not want to use additional clocks in the system Please tell me how can I do this

Thanks
Ackt
 

This sounds to me like you really just want an auto-biased,
capacitor-blocked inverter, and eat the power penalty from
never fully bottoming the input against either rail. Common
approach in RF CMOS for things like prescalers, even at
much lower swings.

Of course there might be other issues like, what happens
when the clock is stopped - the front end might need to
assume a particular state, or maybe you have a pulse train
detector on the side that does power gating, etc.

But seems to me like a comparator capable of running that
fast, would eat as much (or more) power as the inverter.
If you have only a fixed, and perhaps not even critical,
input threshold then start with simple.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top