verilog coding for pipo

please send verilog code for 4bit parallel in serial out shift register

module piso1(sout,sin,clk);
output sout;
input [3:0]sin;
input clk;
wire [3:0]q;
inv u1(p,sl);
and1 u2(n,sin[1],p);
and1 u3(r,sl,q[0]);
or1 u4(s,n,r);
and1 u5(t,sin[2],p);
and1 u6(u,sl,q[1]);
or1 u7(v,u,t);
and1 u8(w,sin[3],p);
and1 u9(y,sl,q[2]);
or1 u10(z,w,y);
dff1 u11(q[0],sin[0],clk);
dff1 u12(q[1],s,clk);
dff1 u13(q[2],v,clk);
dff1 u14(q[3],z,clk);
assign sout = q[3];
endmodule

- - - Updated - - -

module piso1(sout,sin,clk);
output sout;
input [3:0]sin;
input clk;
wire [3:0]q;
inv u1(p,sl);
and1 u2(n,sin[1],p);
and1 u3(r,sl,q[0]);
or1 u4(s,n,r);
and1 u5(t,sin[2],p);
and1 u6(u,sl,q[1]);
or1 u7(v,u,t);
and1 u8(w,sin[3],p);
and1 u9(y,sl,q[2]);
or1 u10(z,w,y);
dff1 u11(q[0],sin[0],clk);
dff1 u12(q[1],s,clk);
dff1 u13(q[2],v,clk);
dff1 u14(q[3],z,clk);
assign sout = q[3];
endmodule

//RTL version

module shiftReg(
clk,
rst,
load, // enable load pIn bus contents into the register
sen, // shift enable
pin,
sout // serial out
);
parameter width = 4;
parameter hi = 1'b1, lo = 1'b0;

input clk, rst;
input load;
input sen;
input [width -1: 0] pin;

output sout;

reg [width -1: 0] sreg;
assign sout = sreg[width -1];
// assign sout = sreg[0]; // For right shift

always @(posedge clk or posedge rst)
if(rst)
sreg <= {width{lo}};
else if(load)
sreg <= pin;
else if(sen)
// what shift reg is needed?
sreg <= {sreg, lo}; // arithmetic shift left
//sreg <= {sreg, sreg[width-1]}; // cyclic shift left
// sreg <= {sreg[0], sreg[width-1:1]; // shift right
else // this branch is optional, some synthesis tools may issue warning
sreg <= sreg;
endmodule // shiftReg