How to avoid glitches at the non-registered output?

Can glitches be avoided?

I use a simple adder core generated by the Xilinx CoreGenerator to do a test,but i find glitches at the Non registered output.
Though the result of registered output is right ,is there anyway to avoid these glitches?

Re: Can glitches be avoided?

Yes its posiible to remove glitches!
This kind of phenomena in digital circuis is known as combinatorial logic
hazard. Here is a link where you can get more help....
**broken link removed**

Re: Can glitches be avoided?

FPGA use LUT for evaluating expressions. The table is simply a truth table. It basically evaluate expression using a ROM structure. The input is taken as an address, and the data at that address in the Look-Up Table (LUT) is output as the result.

Suppose you have 4 inputs, and that you have '0101' at input, and at that address, you have a 1, that you'll see a '1' at output. Suppose you now wish to input '1001'. The problem is that if you change the input value, due to routing delays, it is possible that for a fraction of a second (a few nanoseconds), when passing from '0101' to '1001', you may get a bit ariving faster than the other. So, you may get an intermediate input like '0001' or '1101'. Suppose that the content at address '1001' in the LUT is also 1, but at both addresses '1101' and '0001', you have a zero, then you may get a glitch.

So, for example, it is not good to use combinational logic or LUT as an input of a register CLK input.

Re: Can glitches be avoided?

Glitches can be a problem in low power design in which multiple transitions can waste power. Glitches can also be a problem with asynchonous input such as gated clock, or reset. I think Xilinx recommend clock enable as opposed to gated clock. As for reset, you can have it synchronize by a global clock if that's possible.
For low power design, have all the signal with the most activities grouped in early stages of the combinational logic block to minimize transition in the final stage since the final stage probably has the largest capacitive load.

Other than that, most glitches caused by combinational circuits could be harmless since most of them are clocked out at a register and synchronized with the rest of the system.

For data path, I don't think glitches should be any problem especially they are all in a pipeline.

Re: Can glitches be avoided?

Generally glitches are not such a problem except if you didn't meet timing requirements or you are doing an asynchronous "or multiclock doman" finite state machine. in the first case the problem can be avoided with pipelining for example and in the second case because you might go to a race condition or you want to avoid an undesirable result you may use appropriate coding design like gray-coding or similar treatment, this will save you as well a lot of power but it may need some space, thats all folks

Can glitches be avoided?

The glitchs can't be avoided. But if you implement you design with a sychoronous style , the glitchs are harmless

Re: Can glitches be avoided?

And if you use asynchronous clock domain, another effect, called matastability, will occur. Metastability is practically unavoidable in independent multi-clock domain. What happen is that an input of a flip-flop may flip at the very instent the clk input is triggered. There is a window of about 100~200ps where if that condition occur, the flip-flop output will be ustable (you may get from a 0 to a 1, and back to a zero within the same clock period, or other similar effect).

A way to deal with metastability is to cascade 2 flip-flop, sending the first metastable flip-flop output to a 2nd flip-flop input, and tying the CLK signal together. This introduce a delay of 1 CLK, but filter metastability.

Can glitches be avoided?

So try to use sync design everywhere(as much as possible) in your project. Most glitches are very 'short' time length so that SETUP/HOLD time requirements cannot be satisfied. Therefore, glitches in sync circuit will be filtered and will harmless to your design.

Re: Can glitches be avoided?

agump said:

The glitchs can't be avoided.

Click to expand...

agump,

There are many techniques of glitch avoidance, it doesn't mean that you have a glitch free design but you can avoid the glitch and race condition by many technique for example you may introducing some delays on routing to avoid a possible glitch, u may use some coding technique to avoid glitch occurence. usualky in all synchronous design "one clock" glitchs are of no effect unless they threat the hold and setup time requirements.

Re: Can glitches be avoided?

glitches should b the timing hazzard....there r 2 type....static and the dynamic hazard....

Static hazard - Occurs when it is possible for an output to undergo a momentary transition when it is expected to remain unchanged.
~to eliminate the static hazard, find the adjacent same value in the K-map which is group up, add the consensus term to the minterm. the static hazard can b eliminated...in combinational circuit.


A Dynamic hazard occurs when the output signal has the potential to change more than once when it is expected to make a single transition from 0 to 1 or from 1 to 0.
~dont connect the variable input and its complement to the same level of gate.

hope my explanation isnt tht bad or confusing....i not good at it (explaining) though i understand tht myself- the timing hazard for beginner level...

emmm,,,,the book explain the timing hazard and its ways to eliminate it quite well....i took the part out and upload it hope it helps...

Can glitches be avoided?

for fpga design, based on the LUT nature, the hazard elimination methods are useless, especially for 1-stage LUT.
employing a good sync coding practice will make the glitch harmless as many PROs said here.

Re: Can glitches be avoided?

for synchronous system,...there r also some diffficulties....

the clock skew....the synchronizer failure and metastability...

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Can glitches be avoided?

any body know a book introducing all timing problem involed in digital desing?