VHDL synthesis error using synplify premier

xranger · Jul 26, 2013

Hello,
I encountered a error when I use synplify preimier to synthesis a VHDL design.
the log is

Code:

@E: CD505 :"/filepath/file1.vhd:497:30:497:36|type:Expecting enumeration literal
1 error parsing file /filepath/file1.vhd

and the code in this file1.vhd is:

Code:

497    type  start is (INIT, DEFAULT, ABORT, NOACT);
498   signal start_state : start;

anyone who can help on this? thanks.

FvM · Jul 26, 2013

Not sure, but "default" is a reserved VHDL keyword.

xranger · Jul 29, 2013

Thanks for you reply. But, the Modelsim compilation is OK. I am confused... Dose any features that Synplify not support?

TrickyDicky · Jul 29, 2013

FvM said:
Not sure, but "default" is a reserved VHDL keyword.

No it isnt.
So the problem must be elsewhere - how about posting the full code?