bdh2991
Newbie level 1
I need to create a test bench for a mod 3 counter, however i am new to verilog and i have run into some problems...
i already designed the circuit implementation and it compiled fine. The mod 3 counter is supposed to accept one input, and output the input % 3, treating the first input as the least siginificant bit.
I'm not sure how to go about making a test bench because you can have an infinite number of inputs....
this is the code i have already written:
i already designed the circuit implementation and it compiled fine. The mod 3 counter is supposed to accept one input, and output the input % 3, treating the first input as the least siginificant bit.
I'm not sure how to go about making a test bench because you can have an infinite number of inputs....
this is the code i have already written:
Code:
// JK flip-flop module
module jkff ( j, k, clk, preset, clear, q, q_bar );
input j, k, clk, preset, clear;
output q, q_bar;
reg q, q_bar;
always @ (posedge clk or preset or clear )
begin
if ( clear == 1 ) begin
q <= 1'b0;
q_bar <= 1'b1;
end else if ( preset == 1 ) begin
q <= 1'b1;
q_bar <= 1'b0;
end else if ( j == 1 && k == 0 ) begin
q <= 1'b1;
q_bar <= 1'b0;
end else if ( j == 0 && k == 1 ) begin
q <= 1'b0;
q_bar <= 1'b1;
end else if ( j == 1 && k == 1 ) begin
q <= q_bar;
q_bar <= q;
end else if ( j == 0 && k == 0 ) begin
q <= q;
q_bar <= q_bar;
end
end
endmodule
// MOD 3 module
module mod3 (clk, in, a, b);
input clk, j1, k1, j2, k2, in;
output a, b, q1, q1bar, q2, q2bar;
wire a, b;
wire j1, k1, j2, k2, in;
wire q1, q1bar, q2, q2bar;
assign j1 = ((in & q2bar) | (~in & q2));
assign k1 = 1;
assign j2 = (q1 & ~in);
assign k2 = (~in);
jkff ff1
(
.clk(clk),
.preset(0),
.clear(0),
.j (j1),
.k (k1),
.q (q1),
.q_bar (q1bar)
);
jkff ff2
(
.clk (clk),
.preset (0),
.clear (0),
.j (j2),
.k (k2),
.q (q2),
.q_bar (q2bar)
);
assign a = q1;
assign b = q2;
endmodule