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FPGA DSP based FM radio Receiver Project

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Milruwan

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Sir, I am doing a project on DSP based fm receiver for my final year project.
I want to demodulate the IF signal from the receiver and get the FM multiplex signal. I am using zero crossing as the demodulation method.

Code: 
always @ (posedge sclk)
begin
data_now<=adc_dat;
if((((data_prv<8'd100 )&&(data_now>8'd100))||((data_now<8'd100)&&(data_prv>8'd100))))

begin
data_save<=timer2;
dac_dat<=data_save;
data_prv<=data_now;
cnt_en<=1'b0;
#2 cnt_en<=1'b1;
end

end
Untitled.jpg
According to the zero crossing algorithm I except a specific value for specific frequency but this will give a ramp value, continuously varying value for the output. I attach the oscilloscope view of the input and the output(yellow-input blue-output). I want to get a constant value for specific frequency. Please help me regarding this matter.
 

Isn't it that the timer increment between zero crossings represents signal period, respectively 1/f? Not a high performance FM detector, but it should work as a first approach.

For alternative methods, you may want to review SDR (software defined radio) literatur.

"#2" isn't synthesizable in hardware, by the way. You don't get a pulse in a FPGA implementation.
 
The following code is not resetting at when timer_reset==1'b1 ,Here I
attached the modelsim simulation result. I need to know where I went
wrong. Please help me.

Code: 
module Zero_crossing8 (sclk,sig_in,result);

input sclk,sig_in;
output [7:0] result;

reg [7:0] result=8'b0;
reg [7:0] timer_val=8'b0;
reg timer_reset=1'b0;


always @ (posedge sclk)
begin
	if(timer_reset==1'b1)
		#80 timer_val<=8'b0;
	else
		timer_val<=timer_val+1'b1;
end


always @ (posedge sig_in)
begin
	#100 result<=timer_val;
	#5000 timer_reset<=1'b1;
  #4000 timer_reset<=1'b0;
end

endmodule

[ATTACH=CONFIG]93895._xfImport[/ATTACH]
 

The reset signal isn't active during clock edge.

You said you are targetting to FPGA design, so why don't you start to write synthesizable code? Get rid of the # delay statements.
 

FvM said:
The reset signal isn't active during clock edge.
Click to expand...

What do you mean by this. I am not resetting the FPGA device only checking the register "timer_reset" is 0 or 1.
 

"timer_reset" is sampled at rising clock edge.

I guess you should learn a bit more about about HDL programming.
 

Hi, I have some how manage to detect the zero crossings, but the problem is it is not accurate to detect due to the oscillator clock frequency. I need to know is it possible to change the crystal to 100MHz? I am using the Altera EP2C8Q208C8 Fpga chip. I went several times through the datasheet to determine the Oscillator frequency, but I was not able.

Is Altera EP2C8Q208C8 Fpga chip can be driven with 100MHz crystal?
 

You can use a 100 MHz clock oscillator. Or keep the presently used oscillator and generate a fast clock by a FPGA internal PLL.

I believe that there are better FM decoder algorithms than just measuring zero crossings.
 
FvM said:
I believe that there are better FM decoder algorithms than just measuring zero crossings.
Click to expand...

Thanks for your reply FvM, What are the Other better algorithms that can be easily implement in FPGA?
In theory we learn the following algorithms

1) Zero crossing
2) PLL detection
3) Differentiation

These are the methods I remember . There can be more....
Can you suggest me a easy and accurate method to detect FM ?
 

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