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+notimingcheck option

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chico

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notimingcheck

Whether the +notimingcheck option of NC will affect the simulation result? 3Q
 

+notimingcheck

Of course. If you use +notimingcheck option, when there are setup/hold/timing
happened in your FF, you will not got an "X" (notifier assertion in gate level verilog
library) and warning messages.

My opinion is you should better use +no_notifier instead, which will report setup/hold
time violation but will not change your FF's output into "X", which is good for running gate level design having multiple clock domains.
 

notimingchecks

for simulaitn on gate-level without SDF file, you should with +notimingcheck.
for post-apr simulaiton with SDF file, you should don't with +notimingcheck,
otherwise the simulation should be non-meaningful.
 

verilog notimingcheck

If using notimingcheck, the timing violation would not cause DFF value to 'x', without notimingcheck, the timiing violation would cause DFF to be 'x'
 

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