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generating time delay in vhdl

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venky228

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Hello everyone,

i'm having a small doubt regarding the generation of time delay in vhdl. I'm using ALTIUM NANOBOARD 3000(spartan 3an) for my project.Actually i'm sensing a sinusoidal voltage signal through ADC(8 bit), now i want to generate a time delay of 10 ms for the sensed signal. 'after' statement is not working in synthesis. so plz help me in generating a time delay.

thanks in advance.
 

You need to form a delay line by storing ADC samples in a circular RAM buffer and reading them with a delay.
 

FvM said:
You need to form a delay line by storing ADC samples in a circular RAM buffer and reading them with a delay.
Click to expand...


thanks for your quick reply. but i'm new to coding can u provide me some material or an example on how to do it.
 

I suggest starting with a good VHDL tuturial. You will need to read up on memories and counters.
 

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