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How to layout "bulk" in CMOS ???

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duron999

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Is MOSFET only four terminals: e.g.: "G", "D", "S", "b" ???
i can't find the example in website,
can anyone tell me???

another question is , How can i define where is the "d" and "s"
in layout ??? Thanks !!!
 

MOSFET is 4 terminals as you've written. You need to create an ohmic contact to substrate (NMOS) or n-well (PMOS) to define a voltage on the bulk.

From the layout point of view there's no difference between source and drain.
 

The should be connected as schematic required. But in standard CMOS technology, the bulk terminas of either N or P mosfets (usually N) cannot be connected to different potential.

In layout, the bulk should be as close as to the source. For large current devices, use guarding to prevent latch-up.

The source and drain are usually interchangeable. For NMOS, the terminal with higher potential is drain; for PMOS, higher potential is source.

However, it may be useful to carefully layout with drain/source. For example, if the mosfet has asymmetric source / drain -- as in the case of donut-shape gate and finger-type gate with even number of stripes -- it will be better to choose the terminal with less junction area (thus less parasitic capacitance) as the drain.

Please correct me if I am wrong.
 

what is donut-shape gate and finger-type gate ?
 

There are some layout example can be found on CMOS layout eBooks. You can found that in this forum .
 

xwcwc1234 said:
There are some layout example can be found on CMOS layout eBooks. You can found that in this forum .
Click to expand...

can you give me the book name please, thanks !
 

sadfish said:
what is donut-shape gate and finger-type gate ?
Click to expand...
Please refer to the attached figure.

sadfish said:
can you give me the book name please, thanks !
Click to expand...
A good book is "The Art of Analog Layout"
 

Mosfets might have 4 or 5 terminals. For example, in the N-well process, NMOS will have 4 terminals, which are "S","G","D", and substrate (the same as "bulk"), while the PMOS will have 5 terminals, which are "S","G","D","Bulk" and substrate.
 

lakeoffire said:
PMOS will have 5 terminals, which are "S","G","D","Bulk" and substrate.
Click to expand...

What's the point of p-substrate connection in PMOS? Do you mean there's a contact to the substrate outside of the n-well?
 

Layout of High voltage MOSFET has difference between source and drain.
 

Mosfet is a four terminal device (G , S , D ) and bulk that almost always in nmos case is tied to ground.But in pmos it can be connect to source or vdd.


drain and source are interchangable.
 

borodenkov said:
lakeoffire said:
PMOS will have 5 terminals, which are "S","G","D","Bulk" and substrate.
Click to expand...

What's the point of p-substrate connection in PMOS? Do you mean there's a contact to the substrate outside of the n-well?
Click to expand...

No. But there will be a diode between the p-substrate and the n-well, and as a result, there will be parasitic capacitors. When the bulk is connected to the source, this parasitic cap will affect the performance. In this case, the pmos can be considered as 5-terminal device.
 

May I know how much impact this parasitic cap to the performance of the PMOS?
 

It depond on your requirement.
You can connect the bulk to gnd for NMOS, connect bulk to VDD for PMOS.
Or you can connect the bulk to the source for avoiding the increasing the Vth
 

In standard IC process, connect the bulk of PMOS to VDD and the bulk of NMOS to VSS.
 

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