hfly47
Junior Member level 2
The part of FPGA is V6-XC6VLX760-1, which has 18 clock regions. That clock drives logic in 9 clock regions, and I don't know whether this is the root cause.
And:
1. The number of utilized BUFG is 18, smaller than 32.
2. The number of global clocks in each clock region is smaller than 12.
Thanks a lot.
And:
1. The number of utilized BUFG is 18, smaller than 32.
2. The number of global clocks in each clock region is smaller than 12.
Thanks a lot.
