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[SOLVED] not (~) a single bit in an array in verilog

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sobella1923

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im need to take a not of a single bit in a array of 16.

input [15:0] dat1 =16'b0000001000000001;

what i need is

output [15:0]dat2=16'b0001001000000001;
 

There are several ways you could do this

One way is

Code: 
always @dat1 begin
               dat2 = dat1;
               dat2[12] = ~ dat1[12];
          end
Even though you assign dat2[12] twice, only the last assignment wins. Synthesis tools only synthesize the last assignment.

You could also do

Code: 
assign dat2 = {dat1[15:13], ~dat1[12], dat1[11:0]};
 

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