negative substrate bias: improve or impair performance?

Normally the P-substrate is tied to ground, which is also the lowest potential level found anywhere on the chip.

Negative substrate bias is the situation where the P-substrate is held at a potential lower than any other potential used on the chip (i.e. lower than the potential on any drain, source, gate, or metal layer).

Negative substrate bias has many beneficial effects relating to ESD and latchup, but I'm not concerned with those. What I am interested in is reducing junction capacitance. A negatively-biased substrate increases the size of the depletion region around all the NFET diode junctions, reducing the effective capacitance of these junctions. This should significantly improve switching speed and power consumption.

However there is a countervailing effect: biasing the substrate negative increases the threshhold voltage of the NFETs since it expands the depletion region around their channel. So the voltage at an NFET gate has to rise further before it begins conducting.

Have there been any studies of how these two effects play out against each other, and whether or not it's a net performance/power win to bias the substrate?

I've seen a lot of papers on ESD/latchup benefits, which are nice, but that's not really a major concern for me. I'm also not planning on using local charge pumps to drive the substrate negative locally -- if it's worth it I can afford to bring in a negative potential from off-chip via dedicated pads and metal (this is a low-current path, so the metal doesn't need to be too thick). Technically this "negative potential" will be true ground, i.e. the potential of the case to which the chip is bonded. The "real ground" supplied to the chip's power pads will be slightly positive, and the VDD supplied will be relative to this.

This is for a digital chip, but it's totally full-custom, so I figured posting here rather than the ASIC subforum would be the right approach… it's a digital chip, but this is an analog issue.

PS, I think it's hilarious that the forum's banner ads occasionally display ads for fashion modeling agencies. I guess the search term "modeling" has meaning outside of IC design!

Are you aware that you'd need a more costly dual or triple well process to achieve this?

In a standard CMOS process, all NFETs share the same bulk, i.e. the p-substrate, so all their sources are electrically connected to it.

erikl said:

Are you aware that you'd need a more costly dual or triple well process to achieve this?

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I'm not sure I agree with that.

erikl said:

In a standard CMOS process, all NFETs share the same bulk, i.e. the p-substrate,

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Of course; that's not a problem. In case it wasn't clear I'm talking about creating a negative substrate bias for ALL the nfets on the chip.

erikl said:

so all their sources are electrically connected to it.

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I don't agree with this. An NFET's source and bulk are distinct terminals, and it's quite common for them to be at different potentials. The substrate diode is still reverse-biased (just more so).

quantized said:

An NFET's source and bulk are distinct terminals, and it's quite common for them to be at different potentials. The substrate diode is still reverse-biased (just more so).

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Ok, now I see what you mean. You separate the p+ substrate (bulk) connections from the n+ source connections. In our standard cell layouts these were always touching each other - recommended because of area-saving, but from an electrical view point not necessarily so. Right; should work.

So you'd trade the decrease in parasitic capacitance resp. increase in switching frequency against real estate consumption. Yes, this would work, and the increase of the NFETs' Vth shouldn't matter for digital cells.

erikl said:

Ok, now I see what you mean. You separate the p+ substrate (bulk) connections from the n+ source connections. In our standard cell layouts these were always touching each other

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Who said anything about standard cells? Assumptions like this are why I didn't post in the "ASIC" subforum.

What you describe are "butted well taps"; some foundries prohibit these (i.e. DRC rule against diffusion crossing a select boundary).

erikl said:

Right; should work.

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Of course it will work -- Micron's been doing it with their memory chips (which have small amounts of logic) for at least a decade now.

My question is whether the overall effect on performance is a win or loss. Certainly somebody must have studied this and written a paper about it, but I can't seem to find any. Everything on negative substrate bias seems to be for ESD or latchup, which are the application goals for which Micron has a big pile of patents.

There are some other aspects to this.

First, it's unlikely that the process has been qualified for
Vbs<0*Vds=max. Vbs<0 also has the effect of increasing
Vdb beyond normal. That means higher silicon fields and
more hot carrier generation.

People apply this trick, even so. I proposed it in a conference
short course over 20 years back (for reasons other than what
you mention, and on which I won't elaborate) and the reference
keeps popping up in present-day papers.

How useful this is, in raising speed, depends on how much
of the net output loading is the driving NMOS drain; your
PMOS drain will modulate not at all, neither will the driven
fanout gates' capacitance, so I expect you're playing with
a 10%-type C improvement with the cost of IDsat reduction
that you mention, countering that.

Another issue is that now the substrate is not a neat
ground plane or anything close - it would be actively
driven and distinct from all other electrical goings-on.
It might not bother anything digital, but it could be a
real mixed-signal menace.

dick_freebird, thanks for taking the time to answer; I really appreciate it.

dick_freebird said:

First, it's unlikely that the process has been qualified for
Vbs<0*Vds=max. Vbs<0 also has the effect of increasing
Vdb beyond normal. That means higher silicon fields and
more hot carrier generation.

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Ah, interesting. This chip is for a very unusual application where reliability is not tremendously important (the chips are deployed in huge arrays, and having 10% of them fail is not a problem if it gives a 20% performance increase overall).

dick_freebird said:

and the reference keeps popping up in present-day papers.

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Any chance you might send me the reference? I have access to all the major journals.

dick_freebird said:

How useful this is, in raising speed, depends on how much
of the net output loading is the driving NMOS drain;

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All the performance-critical circuitry is domino logic, so the vast majority of the logic is being done by large NFET-only networks with several diffusion connections. PFETs are only for precharge (not part of the critical path) and output drivers to the next stage (part of the critical path, but relatively lightly loaded).

dick_freebird said:

your PMOS drain will modulate not at all,

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Very true. For this chip I don't think it matters that much. However if it did there's always the possibility of raising the nwell potentials above VDD, which should give the same effect...

dick_freebird said:

so I expect you're playing with a 10%-type C improvement

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Ah, that's slightly disappointing. I was hoping the larger depletion region would reduce the capacitance by more than that.

quantized said:

Who said anything about standard cells?

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I did. Sorry for mentioning these. In our mixed designs we used standard cells for the necessary digital functions.

dick_freebird said:

so I expect you're playing with a 10%-type C improvement

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quantized said:

Ah, that's slightly disappointing. I was hoping the larger depletion region would reduce the capacitance by more than that.

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You could try and estimate the expectable capacitance reduction: with a -1V substrate bias, the cap. reduction of the substrate depletion layer is about 30% (would be 60..70% for -10V bias, estimated from the respective curves by S.M. Sze, Physics of Semiconductor Devices).

Now the overall input cap. reduction depends on the mix between the input caps gate-source, gate-drain, gate-channel and their associated serial substrate capacitances, which - on its part - depends on the process and structure size.

For a given process & design, this could be analyzed by simulation, I think.