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The following is about the ASIC design flow:
Design Specification-->Design Partition-->Design Entry:Verilog Behavioral Modeling-->Simulation/
Functional Verification-->Design Integration and Verification-->Presynchesis Sign-Off-->Synthesize and Map Gate-Level Netlist-->Postsynthesis Design Validation-->Postsynthesis Timming Verification-->
Test Generation and Fault Simulation-->Cell Placement,Scan Chain and Clock Tree Insertion, Cell
Routing-->Verify Physical and Electrical Design Rules
-->Extract Parasitics-->Postsynthesis Timming Verification-->Design Sign-Off-->Production-Ready Mask
While in 90nm and below ,the flow maybe have a little differences.
I suggest you can refer to <Application Specific Integrated Circuit > by John Smith.
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