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Problem with layout of Gain Boosting Op_Amp

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hardyboy_86

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Hi,

I have Layout the design of Gain Boosting Op_Amp but i am experiencing a major issue in post layout that its Unity Gain frequency is going below half of the total,
My gain boosting op_amp is designed for 1.3 GHZ with 77 Degree phase, but in post layout after every effort i managed to get it to 904 MHZ with 65 Degree of phase,,

Plz Let me know what steps should i take to resolve this issue.

Thanks Alot!!
 

It's quite normal that UGF and PM of the layout implementation of RF circuits decrease a lot compared to the schematic. But without showing your current layout you can't get any help here, I'm afraid.
 
2.JPGCapture123.JPG


This is the layout design of Gain Boosting Op_Amp,,
 

Your layouts seem quite good, I think. You could try and analyze the parasitics from the extracted netlist (PEX) and see where you perhaps could decrease them - e.g. by larger distances. Otherwise you'll have to accept a 33% UGF decrease from schematic to layout, I'm afraid. Probably you'll have to develop a ≈2GHz schematic amp to reach the required bandwidth in layout. May be this involves the usage of a process with smaller geometries.
 
Try to resimulate your opamp with "rf" transistors - they including some additional capacitances and are more accurate.
 
Dear erikl
i have already lower the values of output capacitors and got unity gain frequency around ~1.6 GHz with 58 Degree of phase in pre layout, and after re modifying the output path in layout the post layout results are changed to 950 MHz with 65 Degree of phase.
Can you suggest some more tips to increase it more.

Dear Dominik Przyborowski

I'll consider you suggestion and it would be better to use rf transistors if no other method would work.
 

hardyboy_86 said:
Can you suggest some more tips to increase it more.
Click to expand...
  • In schematics, use Dominik's suggestion to simulate with more realistic parasitics.
  • From the extracted layout first check your PEX values and find out which of them contribute most to the UGF decrease.
  • Use smaller W/L ratios, and in any case minimum L .
  • More distance between transistors and guardRing.
 
Dear erikl

Thank You so much for your suggestions , I'll try your suggestions and let you know about the results.

Thanks Alot
 

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