Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to reduce bus switching in the pad?

Status
Not open for further replies.
roger

roger

Full Member level 3
Joined
Aug 27, 2003
Messages
162
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,296
Activity points
1,617
Hi all:
I am looking forward to some algorithms to reduce bus switching
to reduce power consumption. pls give me some idea.
 

I think basically you need to study the behavior
driving circuit of the bus and make sure that the
tristate buffers don't turn on unnecessarily...
 

you can use gray encoding to have a try.



roger said:
Hi all:
I am looking forward to some algorithms to reduce bus switching
to reduce power consumption. pls give me some idea.
Click to expand...
 

I think the internal logic decide the bus switching rate. Maybe you can try cache data in register, fetch data from cache when needed, not from outside through bus.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top