Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[DFTC] Non scan cells in Full scan design

Status
Not open for further replies.

maulin sheth

Advanced Member level 2
Joined
Oct 24, 2010
Messages
502
Helped
90
Reputation
179
Reaction score
90
Trophy points
1,318
Location
Bangalore, India
Activity points
4,161
Hello All,

I have a design..I am trying to insert dft in the netlist..
I am using Synopsys DC Compiler with DFT Compiler from synopsys.
I am using the full scan mux-d style.I want to know that what are the main reasons for not stitching the some flops which are already converted to scan flops after compile -scan.
I have checked the violation...but the same violation is also available for other flops which are stitched perfectly.
Pl help me to solve this problem.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top