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Warning: vsim-3106 Port type is incompatible with connection (port 'clock')

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nervecell_23

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Hi,

The title is a warning given by ModelSim when I start the simulation.
The problem is I'm pretty sure all the port type of my clock signal is the same, namely 'input'.
Plus this warning didn't exist in the previous simulation and came out from nowhere after some modifications to the components which is completely irrelevant to the indicated region.

Any suggestion is appreciated.

Thanks
 

It would help to show the complete error message and the relevant lines of code around the line generating the error.

Check out my post on Wires versus reg.
 

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