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metal resistance of power MOS FET

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xuedashun

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I have a big power MOS FET and Ron is about 50m ohm. The routing metal wires (metal 1/2/3/4..and via ) on the layout
generate some parasitic resistance. I don't know how much the metal resistance could be.

Is 5 mohm good estimation? (In my case 5 mohm is about 10% of the power FET Ron: 50mohm *10%=5 mohm)

Thanks for your help！
 

Many power MOSFETs I have seen, fly source bond wires
into the core of the chip face. And they tend to use 10
mil wire, or today even ribbon bonding. This aspect is
very variable, by construction.

I'd say allotting 10-20% of total Ron to the wiring (chip,
bond, leadframe) is sensible enough. You might find more
insight by reading vendors' SPICE models, where they
will often break up the conduction path to insert Ls, Cs
and Rs realistically and leave clues as a result.
 

Don't you have the technology documents to find out how much is the resistance per square of each metal?
It will really depend on how long and wide your metal routing is throughout the different levels!
In my opinion, obtaining an estimation from Ron is far from accurate...
 

dick_freebird,

Thanks for your response.

You are saying 10-20% of Ron for whole wiring (chip, bond, leadframe). Here I only want to know
the parasitic metal(metal 1/2/3/4 and via) resistance because there kevin connection on the power
FET so bond and leadframe's voltage drop is common-mode voltage.

Do you think 6% of Ron is good estimation for just the metal resistance? Thank you!


dick_freebird said:
Many power MOSFETs I have seen, fly source bond wires
into the core of the chip face. And they tend to use 10
mil wire, or today even ribbon bonding. This aspect is
very variable, by construction.

I'd say allotting 10-20% of total Ron to the wiring (chip,
bond, leadframe) is sensible enough. You might find more
insight by reading vendors' SPICE models, where they
will often break up the conduction path to insert Ls, Cs
and Rs realistically and leave clues as a result.
Click to expand...
 

In one of my power IC designs the metallization resistance
was about half of the overall. IC flows are not as nice as
power FET (discrete) processes, for metal thickness (or,
for having the current flow vertically and using the whole
die backside as one terminal).
 

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