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Scan chain insertion basics

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mvvijay78

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scan insertion tutorial

Hi,
I am very new to the concept of DFT.I would like to know is once the RTL guy finishes his coding and gives the code to the DFT person what exaclty does the DFT team do.I am aware of the normal flow form RTL to GDSII but not comfortable with the DFT flow.
One more doubt i have is that whetether all the flipflops in the design would be replaced by scan flipflops.
Also what are the constrinmats to be given while doing the scan chain insertion?
Can anyone please throw light on this
Regards
Vicky
 

scan chain insertion

clock-generated related flip-flops should not been replace with scan-DFF,
the constraint is same with function while insert scan-chain.
and you shoud set ideal net to scan_en because it should connect to SE pin of flip-flops after scan-chain inserted, the fanout is too big.
But you need wirte a constraint for test-mode.it should reflect test environment.
 

scan insertion

search this site for scan tutorial. A while back someone uploaded a good demo for learning jtag/dft concepts. look at those to get some idea. generally DFT tools such as dftadvisor from mentor rips out all flip flops from design and replaces tham with their scan equivalant scan flops available in vendor libraries. there are lots of rules and guideline for doing this. look at mentor DFT advisor for these rules and guidelines. The idea behind DFT is to be able to write test vectors to verify a silicon on the tester so you can sort and isolate faulty ones.
 

scan chain tutorial

Pop into your Design Compiler installation directory and copy the DFT manuals. There are both manuals and tutorials...

AFAIK, if your design is plain, meaning a digital circuit comprises of only flipflops and combinational cells, without latch/tristate/RAM/macro/etc, test insertion is trivial, no more than a few lines and some extra simulation steps...

ATPG for plain designs is also simple, Tetramax has already done everything...
 

dft scan chain

For scan insertion, DFT engineer usually will work with design engineer to define the scan in, scan out, scan enable, scan clock ports and number of scan chain required, all these are test constraint required for scan insertion.
In general, the dft tools will use your test constraint provided,
1) replace all your normal flops with scan flops (flop with dont touch attribute will not be replaced).
2) Stitched all the scan flops together to a number of scan chain specify.
3) ATPG tools will then use to generte the test vectors for the design.
 

tetramax tutorial

which Eda tools are best for DFT. Cadence , Mentor or Synopsys
 

scan chain basics

Most people use the Synopsys Tetramax for DFT.
 

synopsys tutorial scan insertion

"Tetramax for DFT"???
I think you should learn more about DFT.
My dear friends, if you want to know DFT, i advice you read DC, DFT workshop of synopsys. These will help you.
 

scan insertion

scan insertion tools atpg tools
snps DC TetraMax
DFT advisor Fastscan
syntest
CADence RTl_compiler
 

define a specific scan chain

i think synopsys is better.
 

synopsys scan insertion

so to solvnet.synopsys.com ,
lot of material is avilable for newbies.
 

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