mano1988
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Hi,
I am making use of the PMOD AD1 (AD7476-12bit) for my application. I have used a FSM to interface the PMOD to the FPGA.
From the timing diagram from the data sheets available, the ADC's poweron is dependent on the nCS signal.
And I have a doubt that what would happen to the data converted (SDATA), if the nCS pin is pulled up even before the conversion is over? In other words, what if the ADC is powered off, before the conversion is over?
The data sheet reads like as soon as the nCS signal is pulled up the SDATA would get into tri-state, does that mean that the improperly converted data would be flushed into the FPGA.
Thank You,
M.Manoj
I am making use of the PMOD AD1 (AD7476-12bit) for my application. I have used a FSM to interface the PMOD to the FPGA.
From the timing diagram from the data sheets available, the ADC's poweron is dependent on the nCS signal.
And I have a doubt that what would happen to the data converted (SDATA), if the nCS pin is pulled up even before the conversion is over? In other words, what if the ADC is powered off, before the conversion is over?
The data sheet reads like as soon as the nCS signal is pulled up the SDATA would get into tri-state, does that mean that the improperly converted data would be flushed into the FPGA.
Thank You,
M.Manoj