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Problem with VHDL code

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stijn58274

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Hi,

I am learning VHDL last weeks. Im now making an attenuator for audio samples. I want to attenuate 12 bits audio samples.
But when I want to simulate in Modelsim I get the following error:
Identifier "unsigned" is not directly visible.


Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;


ENTITY attenuator IS
   PORT( 
      out       : OUT    std_logic_vector (11 DOWNTO 0);
      input     : IN     std_logic_vector (11 DOWNTO 0);
      validdiv: IN std_logic
   );

-- Declarations

END attenuator ;

--
ARCHITECTURE attenuate OF attenuator IS
signal b:integer;
signal c:integer;
signal d: std_logic_vector(11 downto 0);

BEGIN
  process (input,validdiv)
    begin
	if rising_edge(validdiv) then
	 b <= conv_integer(unsigned(input));
	 c <= b/4;
	 d <= conv_std_logic_vector(c, 12);
    out <= d;
    end if;
end process;
  
END ARCHITECTURE attenuate;

Can somebody help me please?
 

Why do you define "out" and "in" as std_logic_vector when you want them to be unsigned ?
Also, "validdiv" serves as a clock to your flip-flop. this is bad.
You should use your system clock and "validdiv" as an enable signal.
 

You should use either std_logic_arith or numeric_std never both
 

the std_logic_arith and numeric_std both define unsigned type, so you cannot see either without being explicit

eg:
signal my_us : numeric_std.unsinged(3 downto 0);

To avoid this, you should not use the non-standard std_logic_arith library, and stick withe the IEEE standard numeric_std instead.
 

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