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verilog-A genvar for-loop problem

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edwina

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Hi
I'm making some code and trying to use genvar but Cadence gives some error back. I suspect what the problem is but I'm not sure. Furthermore I hope someone of you encountered this problem before and has knows a workaround
The code is a little complicated and a there is a lot of stuff in it that isn't important for you guys (and most of it comes out of a scientific paper, so I think i'm not allowed to publish it here), but the basic structure is:
Code:
`include "disciplines.vams"

module model2v3(anode, cathode, photon);
inout anode, cathode, photon;
electrical anode, cathode, photon, gnd;
ground gnd;

[branch declarations]

[some paramter and variable declaration]
genvar k, h;

analog begin

[other stuff]

for(k = 1; k <= TrapAmount; k = k + 1)
begin
	@(timer(tcr[k]))
	begin

	[some if else statements, forloops and other things]

	end
end

[more stuff]

end
end module

But Cadence (5.1.41) gives me some error:
  • ERROR (VACOMP-1168): "for(k = 1; k <= TrapAmount; k = k + 1)<<--? "
    "***", line 157: Encountered an invalid for-loop control statement. The genvar expression must consist of an integer constant or other unrolled genvar variable expression only.
  • ERROR (VACOMP-2191): "***",
    line 157: Encountered invalid for loop. Check the genvar variables in the for loop.
  • ERROR (VACOMP-2215): "@(timer(tcr[k]<<--? ))" "/****"
    line 159: Encountered incorrect reference to genvar variable `k' in multi-layer for loop. Check that the access is in the corresponding for loop.

I've made a test file to check where it could go wrong and I suspect the problem is because of the variable "TrapAmount" in the for declaration. Without using genvar this for declaration doesn't give any errors but when using genvar it does (and when I replace "TrapAmount" by e.g. 6 the errors disappear). Could someone confirm this is true? And second question: Is there a way to use a variable in the declaration of a genvar forloop without problems?
 

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