muneebziaa
Newbie level 5
Hi Experts,
I am using Virtex 4 ML403 Evaluation Platform FPGA kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the ADC to DAC or connect input to the output.
As much I could understand the setting of register to send the analog data from the folloeing two paths avaliable:
PATH # 1:
INPUT PATH :
"DATA ON INPUT JACK ==> RECORD SELECT MUX ==> RECORD GAIN ==> ADC ==> ANALOG SAMPLE RATE ==> AC LINK INTERFACE ==> SDATA_IN ==> FPGA PIN "
OUTPUT PATH:
# 1 IF POP IS EQUAL TO ZERO= "FPGA PIN ==> DAC SAMPLE RATE ==> PCM OUT VOLUME ==> NATIONAL 3D SOUND ==> OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT."
# 2 IF POP IS EQUAL TO ZERO= "FPGA PIN ==> DAC SAMPLE RATE ==> PCM OUT VOLUME ==> BY PASSING NATIONAL 3D SOUND ==> OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT."
PATH # 2:
INPUT PATH # 1:
IF DATA IN IS FROM MIC= "DATA ON INPUT JACK ==> PASSED FROM REGISTER 0Eh IN ANALOG FORM ==> NATIONAL 3D SOUND ==> TO OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT "
INPUT PATH # 2:
IF DATA IN IS FROM LINE_IN= "DATA ON INPUT JACK ==> PASSED FROM REGISTER 10h IN ANALOG FORM ==> NATIONAL 3D SOUND ==> TO OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT ".
Now I have above mentioned two path from which I am interested in PATH # 1, mean while I am able to stop PATH # 2 by setting the register relating in PATH # 2 which are:
REGISTER = 0Eh , value = 8000 (MIC MUTED)
REGISTER = 10h , value = 8808 (LINE_IN MUTED)
as these two registers are used to provide gain for the PATH # 1 so by setting them to these values will shut this path down.
OK NOW I HAVE SET THE FOLLOWING REGISTERS IN FOLLOWING MANNAR TO SET THE PATH # 1 AS MY USING PATH:
REGISTER = 1Ah ,NAMED = RECORD SELECT, value = 0404 (USING LINE_IN AS MY INPUT SOURCE).
REGISTER = 1Ch ,NAMED = RECORD GAIN, value = 0000 (12 dB GAIN OF THE INPUT SIGNAL FEED TO THE ADC).
REGISTER = 04h ,NAMED = HEADPHONE VOLUME, value = 0000 (0 dB ATTENUATION FOR THE OUTPUT SIGNAL).
REGISTER = 0Ah ,NAMED = PC BEEP, value = 8000 (MUTED).
REGISTER = 20h ,NAMED = GENERAL PURPOSE, value = 2080 (NATIONAL 3D SOUND SYSTEM AND LOOPBACK IS ON )
REGISTER = 18h ,NAMED = PCM OUT VOLUME, value = 0000 (12 dB GAIN OF THE OUTPUT SIGNAL COMING FROM THE DAC).
MY QUESTION:
A register named POWERDOWN CONTROL / STATUS REGISTER (26h) has the four LSB which show the following configration when read:
BIT# BIT Function: Status
0 ADC 1 = ADC section ready to transmit data
1 DAC 1 = DAC section ready to accept data
2 ANL 1 = Analog mixers ready
3 REF 1 = VREF is up to nominal level
WHEN I READ THESE REGISTERA ONLY MY BIT # 3 & 1 ARE HIGH WHILE BIT # 2 & 0 ARE NOT... WHY IS THAT??
I have mentioned everything I know about this IC configation, I have mentioned paths and there control register, can anyone help me to set my PATH # 2 properly and show me how to set BIT # 2 & 0 of register 26h high so that I could Complet my ADC to DAC path.
I would be thaknful to you
Regards.
Muneeb Ziaa
I am using Virtex 4 ML403 Evaluation Platform FPGA kit, on this kit a product of TI is used for audio data converting named LM4550. This IC work on the AC 97 CODEC which take serial data as an input and output. This IC work on different 16 bit registers to route data either through the ADC to DAC or connect input to the output.
As much I could understand the setting of register to send the analog data from the folloeing two paths avaliable:
PATH # 1:
INPUT PATH :
"DATA ON INPUT JACK ==> RECORD SELECT MUX ==> RECORD GAIN ==> ADC ==> ANALOG SAMPLE RATE ==> AC LINK INTERFACE ==> SDATA_IN ==> FPGA PIN "
OUTPUT PATH:
# 1 IF POP IS EQUAL TO ZERO= "FPGA PIN ==> DAC SAMPLE RATE ==> PCM OUT VOLUME ==> NATIONAL 3D SOUND ==> OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT."
# 2 IF POP IS EQUAL TO ZERO= "FPGA PIN ==> DAC SAMPLE RATE ==> PCM OUT VOLUME ==> BY PASSING NATIONAL 3D SOUND ==> OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT."
PATH # 2:
INPUT PATH # 1:
IF DATA IN IS FROM MIC= "DATA ON INPUT JACK ==> PASSED FROM REGISTER 0Eh IN ANALOG FORM ==> NATIONAL 3D SOUND ==> TO OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT "
INPUT PATH # 2:
IF DATA IN IS FROM LINE_IN= "DATA ON INPUT JACK ==> PASSED FROM REGISTER 10h IN ANALOG FORM ==> NATIONAL 3D SOUND ==> TO OUTPUT JACKS EITHER HEADPHONE OR LINE_OUT ".
Now I have above mentioned two path from which I am interested in PATH # 1, mean while I am able to stop PATH # 2 by setting the register relating in PATH # 2 which are:
REGISTER = 0Eh , value = 8000 (MIC MUTED)
REGISTER = 10h , value = 8808 (LINE_IN MUTED)
as these two registers are used to provide gain for the PATH # 1 so by setting them to these values will shut this path down.
OK NOW I HAVE SET THE FOLLOWING REGISTERS IN FOLLOWING MANNAR TO SET THE PATH # 1 AS MY USING PATH:
REGISTER = 1Ah ,NAMED = RECORD SELECT, value = 0404 (USING LINE_IN AS MY INPUT SOURCE).
REGISTER = 1Ch ,NAMED = RECORD GAIN, value = 0000 (12 dB GAIN OF THE INPUT SIGNAL FEED TO THE ADC).
REGISTER = 04h ,NAMED = HEADPHONE VOLUME, value = 0000 (0 dB ATTENUATION FOR THE OUTPUT SIGNAL).
REGISTER = 0Ah ,NAMED = PC BEEP, value = 8000 (MUTED).
REGISTER = 20h ,NAMED = GENERAL PURPOSE, value = 2080 (NATIONAL 3D SOUND SYSTEM AND LOOPBACK IS ON )
REGISTER = 18h ,NAMED = PCM OUT VOLUME, value = 0000 (12 dB GAIN OF THE OUTPUT SIGNAL COMING FROM THE DAC).
MY QUESTION:
A register named POWERDOWN CONTROL / STATUS REGISTER (26h) has the four LSB which show the following configration when read:
BIT# BIT Function: Status
0 ADC 1 = ADC section ready to transmit data
1 DAC 1 = DAC section ready to accept data
2 ANL 1 = Analog mixers ready
3 REF 1 = VREF is up to nominal level
WHEN I READ THESE REGISTERA ONLY MY BIT # 3 & 1 ARE HIGH WHILE BIT # 2 & 0 ARE NOT... WHY IS THAT??
I have mentioned everything I know about this IC configation, I have mentioned paths and there control register, can anyone help me to set my PATH # 2 properly and show me how to set BIT # 2 & 0 of register 26h high so that I could Complet my ADC to DAC path.
I would be thaknful to you
Regards.
Muneeb Ziaa