Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Multifingered transistor - gds

Status
Not open for further replies.
G

georgemailo

Newbie level 4
Joined
Apr 26, 2012
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,323
Hello everyone,
I want to design a current steering DAC where each unit current cell is composed by one current source transistor, one cascode transistor and one switch transistor. My goal now is to increase the output impedance.
As I have understood, if I have a single fingered transistor with a certain width and length then by using 2 fingers I essentially double both width and length. Right? Shouldn't that also mean that by increasing the number of fingers I should get lower gds? In my case the gds, actually, increases slightly by increasing the number of fingers. What do I miss? Can you suggest me any effective way of increasing the output impedance?
Thank you.
 

georgemailo said:
As I have understood, if I have a single fingered transistor with a certain width and length then by using 2 fingers I essentially double both width and length. Right?
Click to expand...
No. The individual fingers of a transistor are in parallel. So you double/multiple its width but not its length. Length stays the same, you increase W/L .

georgemailo said:
Shouldn't that also mean that by increasing the number of fingers I should get lower gds? In my case the gds, actually, increases slightly by increasing the number of fingers.
Click to expand...
Right: Larger W/L --> larger gds and lower output impedance

georgemailo said:
What do I miss? Can you suggest me any effective way of increasing the output impedance?
Click to expand...
For this, you'd have to connect transistors in series, by that increasing their effective length, decreasing the W/L ratio --> lower gds and higher output impedance.

Even better: use real cascoding: a serial circuit of 2 transistors, the first one in source-based (SB) configuration, the second one in gate-based (GB) configuration. This will increase the output impedance even more, because the output impedance of a GB transistor configuration is considerably higher than that of a SB config.
 

Thank you for your answer. It was very helpful!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top