Help me fix this code for SRAM block

Help in SRAM block??

I dont know where i went wrong in the following code,when i simulate the
code...i am getting RWD <= "UUUUUU"in the waveform results....

entity SRAM is
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end SRAM;

architecture behaviour of SRAM is
begin
process(BNKSEL,RDCAS,WRCAS,CADDR,RADDR,RWD)
subtype tmp is std_logic_vector(15 downto 0);
type memory_array is array(integer range 0 to 127,integer range 0 to
15);---128 rows and 16 columns
variable mem : memory_array;
begin
if(BNKSEL'event and BNKSEL = '1') then
if(RDCAS = '1') then
RWD <=mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR)));
DTRDY <= '1';
end if;
if(WRCAS = '1') then
mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR))) :=
RWD;
DTRDY <= '0';
end if;
end if;
end process;
end behaviour;


TESTBENCH :
------------

entity tb_SRAM is
end tb_SRAM;

architecture tb of tb_SRAM is
component SRAM
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end component;
signal RDCAS,WRCAS,DTRDY,BNKSEL : std_logic;
signal CADDR : std_logic_vector(6 downto 0);
signal RADDR : std_logic_vector(3 downto 0);
signal RWD : std_logic_vector(15 downto 0);
begin

UUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);

CADDR <= "0010010";
RADDR <= "0010";
RWD <= "0001000100010001";
BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 30
ns;
RDCAS <= '0','1' after 26 ns,'0' after 34 ns;
WRCAS <= '0','1' after 10 ns,'0' after 18 ns;

end tb;

Re: Help in SRAM block??

Are you sure ur code is compiling clean???
I am getting compilation error for following line in code!!!

type memory_array is array(integer range 0 to 127,integer range 0 to 15);


Why are you trying to use two dimensional array for memory!
Only single dimension array is sufficient!

You can get free SARM VHDL models from SRAM manufaturers
search on web you get tons of model for study!

Re: Help in SRAM block??

I compiled the code in NC-Sim ...i did not get any compilation error...

i need to use a memory matrix with 128 rows and 16 columns..because of this reason..i am using two-dimensional array..


regards,
dcreddy1980

Re: Help in SRAM block??

Hi,

It is normal for you to get "U" in simulation since the memory array you're
creating is not initialized.

Re: Help in SRAM block??

Hi,
I tried and modified your code to make it compilable. Now its compiling and giving proper results. Still the coding style is not efficient and enough to be called as SRAM. You need to have a reset pin as well. Almost every chip requires power-on reset, where you initialize all required signals.
Reason why you were getting 'U' is in the basics of VHDL as well as SRAM.
As SRAM has same data-bus for read as well as write, you need to force 'Z' from DUT on bus during write operation to allow external module to force data on bus (external module can be TB or Memory Controller). This is clearly mentioned in SRAM data sheets, data bus goes 'Z' during write operation. Also after reading data bus goes 'Z' after a specific time which is mentioned in data sheets to allow next operation to be performed.
As far as VHDL is concerned you were forcing data on RWD from DUT as well as TB so it is case of Multiple drivers of signal.
Also I suggest you to use Named Association instead of Positional Association for port mapping, it helps in bigger designs.
see the modified code below:=

==============================================
LIBRARY IEEE ;
USE ieee.STD_LOGIC_1164.all ;
USE ieee.STD_LOGIC_arith.all ;
USE ieee.STD_LOGIC_unsigned.all ;


entity SRAM is
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end SRAM;

architecture behaviour of SRAM is
begin
process(BNKSEL,RDCAS,WRCAS,CADDR,RADDR,RWD)
subtype tmp is std_logic_vector(15 downto 0);
type memory_array is array(integer range 0 to 127,integer range 0 to 15) of tmp; ---128 rows and 16 columns
variable mem : memory_array := (others =>(others => (others => '0')));
begin

if(BNKSEL'event and BNKSEL = '1') then

if(RDCAS = '1') then
RWD <=mem(conv_integer(unsigned(RADDR)),conv_integer(unsigned(CADDR)));
DTRDY <= '1';
else
RWD <= (others => 'Z');
end if;

if(WRCAS = '1') then
mem(conv_integer(unsigned(RADDR)),conv_integer(unsigned(CADDR))) := RWD;
DTRDY <= '0';
end if;

elsif(BNKSEL'event and BNKSEL = '0') then
RWD <= (others => 'Z');
end if;
end process;
end behaviour;
==============================================
--TESTBENCH :
--------------
LIBRARY IEEE ;
USE ieee.STD_LOGIC_1164.all ;
USE ieee.STD_LOGIC_arith.all ;
USE ieee.STD_LOGIC_unsigned.all ;

entity tb_SRAM is
end tb_SRAM;

architecture tb of tb_SRAM is
component SRAM
port(CADDR : in std_logic_vector(3 downto 0);
RADDR : in std_logic_vector(6 downto 0);
RWD : inout std_logic_vector(15 downto 0);
BNKSEL : in std_logic;
RDCAS : in std_logic;
WRCAS : in std_logic;
DTRDY : out std_logic);
end component;
signal RDCAS,WRCAS,DTRDY,BNKSEL : std_logic;
signal CADDR : std_logic_vector(3 downto 0);
signal RADDR : std_logic_vector(6 downto 0);
signal RWD : std_logic_vector(15 downto 0) ;
begin

UUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);

RADDR <= "0010010";
CADDR <= "0010";
RWD <= (others => 'Z'), "0001000100010001" after 22 ns, (others => 'Z') after 28 ns;
BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 32 ns, '1' after 40 ns,'0' after 48 ns;
RDCAS <= '0','1' after 6 ns,'0' after 10 ns, '1' after 37 ns, '0' after 43 ns;
WRCAS <= '0','1' after 22 ns,'0' after 28 ns;

end tb;
==============================================

Compile and Run it, check if it is serving your purpose. Feel free to post any questions.

Regards,
Jitendra