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Can I design 10G VCO using TSMC 0.18um?

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dd2001

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10g vco

I've designed a 10GHz VCO(LC tank) in TSMC 0.18um, however, phase noise is very poor, -85dbc at 1Mhz, can't meet specs. Does anyone know it's possiable to design such VCO with TSMC 0.18um process?
 

did you stop the noise coming from the tail current source ?
 

The process can match you request. Try it
 

I have a fren who is doing the same thing. he is able to meet the spec. therefore i think u can do it too.
 

I tried to do this in the past but found out as you have that even though the cells in tsmc library can switch at speed close to 650mhz but they have terrible jitter at speeds above 300mhz. I ended up using cadence tool to design the cells mostly uning transmission gates. if you look into tsmc cells, for example a 2-1 mux you see six levels of logic which leads to excess noise at higer speeds. in a 2-1 mux designed with t-gate, logic depth is only two which is better for noise.
 

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