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Synthesis of RAM in Cadence RTL

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KHDAK

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Hi,

I have technology library for 2048x32 RAM and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this RAM as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file for this RAM or is it fine to just define it as a component in my code?
 

You do not need a VHDL file for the ram, just a liberty for this ram.
And a libert for the std cell.
 
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    KHDAK

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ok but I am getting a message that RAM component is inferred as a logic abstract and I also can't see that logic inside RAM block in schematic view.
 

You should not see any logic inside the RAM is this one has a liberty associated.
 
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