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Label short in Cadence Virtuoso

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tromeros

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Hi,
I have designed a spiral inductor in Cadence Virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between the ports, which makes sense since the ports are on the edges of the inductor.
My question is what should I do to pass succesfully the LVS?
Thanx in advance!
 

You can use an additional dummy layer covering this inductor and introduce a new element in LVS comand file.
 

Hi Fom,
can you be a little bit more specific?
You say to use a dummy layer. The whole structure uses metal 4 and metal 3 for the underpass. The dummy layer where should it be placed and what kind of metal should it be? And what about the pins ? They will still form a short.
Thanx a lot. I appreciate any further details.
 

Add a marker layer to mark the inductor. The marked metal should be substracted from the original metal to form connections.
AND INDMARK METAL4 IND
NOT METAL4 IND METAL4A
Use METAL4A for connections.
 

Hi again,
in my process there is no marker layer. I use AMS035 process.
I found only an INDDEF layer to define the inductor. However the error persists.
I ve seen also in other posts that I should use an INDDUMMY over the inductor. I dont have such layer.
In your answers please be as explain in much detail because I m still a beginner in virtuoso.
Thanks a lot.
 

INDDEF, INDMARK, INDDUMMY.
I think all of them are the same: INDUCTOR definition.
But if you have INDDEF layer that means INDUCTOR may be already defined in your LVS command file. Check you LVS command file. If it uses INDDEF layer?
If so may be you have real short in layout.
Debug you LVS on simple layout that includes the INDUCTOR only.
 

Hi, first of all I want to thank you for your help but I still have difficulties to overcome the problem. I will be more specific so that you can help me better.
I am using a metal 4 cmos ams process. I can only define INDDEF layer and not INDDUMMY or INDMARK. I suppose that they are the same. For LVS and DRC,RCX I use assura.
So I create an INDDEF layer that covers the whole structure. Then, what should I do? Where should I write in the assura environment the commands that you say in your posts?
Please explain in detail.
Thanx a lot, again :)
 

In gds add dummy layer

In rule file your must add the rule for inductor
like resistor you can't a metal for 2 name
this is for lvs lpe for extract

Alcohol
 

is there a way to design inductors with TSMC30 process because it does not have any of the layers that have been mentioned??
 

If you want, you can add the mark layer by yourself.
 

Hughes said:
If you want, you can add the mark layer by yourself.

how do i do that????
 

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