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SystemC is more on higher abstraction level then VHDL and Verilog. SystemC can be used on specification level, architecture level. where as VHDL and verilog are more on behavioral level and below. The biggest advantage of SystemC over VHDL and other HDLs is that it supports co-simulation of software firmwares and hardware designs/components. which is not possible in VHDL. SystemC is based on C++ class libraries. Another advantage is systemC is a opensource application, and can be used free of cost. most of the sophisticated HDL tools are not free. for further information you can look on https://www.accellera.org/downloads/standards/systemc/about_systemc/
Actually SystemC is used for entirely different motive rather than other HDL.
It mainly used for System Modeling,Architectural exploration,virtual protyping for software development.
SystemC modeling is done before RTL(using HDL) to confirm whether the IP we are going to implement in RTL is feasible or not.And it takes very less time and less effort as compared to RTL.
SystemC does have one strength at the RTL level for modeling DSP, image processing or any design that needs to experiment with fixed precision arithmetic. The C++ type system makes it easy to write and very efficient. But once you get into lots of bit-level manipulations, that's where the HDL start to become more efficient.
I disagree with one comment in the previous post. You can use HDLs to co-simulate with your software/firmware. It just that it is not efficient enough to be a platform to verify your software/firmware. But you can certainly use it to verify the communication between hardware and software.
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