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measured power twice the simulation result

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guow06

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I used a high voltage technology for my chip and violated some latch-up design rules. The measured power consumption is around 50 mA which is twice the simulation result.
What could be the potential reasons for that? ( my chip is pretty big and complex, so if latch-up happens, it should burn the chip instead of causing extra power. Is that correct? what else can I blame?)
 

Yes, if latch-up occurs it will short the supply to common. So the high power consumption is likely due to a different problem. Hard to say what that could be. Troubleshooting that kind of problem on an IC can be difficult so good luck with that ;-).
 

Sure it is. I have no idea what could the reason be. I have a chance to put a test structure on a test chip, so I have to think what structure is appropriate.

crutschow said:
Yes, if latch-up occurs it will short the supply to common. So the high power consumption is likely due to a different problem. Hard to say what that could be. Troubleshooting that kind of problem on an IC can be difficult so good luck with that ;-).
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