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I don't really understood your response.
1- first we run simulation at RTL level to check the functionality
2- LEC is used to garantee the functionality is the same between the RTL and all netlists generated during the backend flow.
3- the gate simulation is done to check the timing (ovelap with STA)
LEC is here to check the RTL code is properly read/understood by the synthesis tools.
And as RTL verifier, I will never said, I check everything cases , then LEC is here to just to said, your final netlist is identical as your RTL, but your RTL simulations could have some weak points.
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, then LEC is here to just to said, your final netlist is identical as your RTL, but your RTL simulations could have some weak points.