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How to estimate the SRAM area?

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aspirinnnnn

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hi,everyone,I want to know how to estimate sram area in ASIC

for example, I want to implement a two port (one for read ,one for write ) sram in ASIC , and the depth is D, words width is W , in a certain technology, how to estimate the area ?
 

Well, is it really dependent of the RAM provider, it is better to have the ram compiler, to generate the data sheet/ LEF file to have a better area number
 

thanks very much, I still want to know how to estimate the area by hand, may be the estimation is roughly right or relatively right will be ok

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thanks very much, I still want to know how to estimate the area by hand, may be the estimation is roughly right or relatively right will be ok
 

You can see general details (depend on technology)
At
**broken link removed**
 

I dont think there is an easy way to do that by hand. A couple of things you can do is find out the bit cell which you are using. That will determine the bit cell area. Now the periphery and control logic depends on the design and speed of the RAM. For high speed there might banks of bitcell and more complex logic. For simple designs you can 20% to bit cell area and estimate the area. But there is no hard and fast rule for doing this.
 

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