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    how to eliminate the warnings in gate level simulation

    hi all,
    i am getting warnings while i do gate level simulation i am including the errors and the mapped netlist of my design



    Warning-[SDFCOM_IWSBA] INTERCONNECT will still be annotated
    alu.sdf, 37
    module: alu, "instance: stimulus.me"
    SDF Warning: INTERCONNECT from a to U464.IN2 has Continuous Assignment at
    alu_mapped_netlist.v:38, delay will still be annotated.


    Warning-[SDFCOM_IWSBA] INTERCONNECT will still be annotated
    alu.sdf, 46
    module: alu, "instance: stimulus.me"
    SDF Warning: INTERCONNECT from a to U458.INP has Continuous Assignment at
    alu_mapped_netlist.v:38, delay will still be annotated.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 825
    module: XOR2X1, "instance: stimulus.me.U461"
    SDF Warning: IOPATH from IN1 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 826
    module: XOR2X1, "instance: stimulus.me.U461"
    SDF Warning: IOPATH from IN1 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 827
    module: XOR2X1, "instance: stimulus.me.U461"
    SDF Warning: IOPATH from IN2 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 828
    module: XOR2X1, "instance: stimulus.me.U461"
    SDF Warning: IOPATH from IN2 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 1079
    module: XOR2X1, "instance: stimulus.me.U435"
    SDF Warning: IOPATH from IN1 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 1080
    module: XOR2X1, "instance: stimulus.me.U435"
    SDF Warning: IOPATH from IN1 to Q is not found.


    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 1081
    module: XOR2X1, "instance: stimulus.me.U435"
    SDF Warning: IOPATH from IN2 to Q is not found.

    All future warnings not reported; use +sdfverbose to report them.

    Warning-[SDFCOM_INF] IOPATH not found
    alu.sdf, 1082
    module: XOR2X1, "instance: stimulus.me.U435"
    SDF Warning: IOPATH from IN2 to Q is not found.


    Total errors: 0
    Total warnings: 76


    alu_mapped_netlist.v
    Code:
    `include "saed90nm.v"
    module alu ( out, co, a, b, cin, clk, bi, sel );
      output [3:0] out;
      output [3:0] co;
      input [3:0] a;
      input [3:0] b;
      input [3:0] sel;
      input cin, clk, bi;
      wire   N121, N192, N270, N271, N272, N273, N274, n48, n49, n50, n54, n55,
             n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n67, n69, n70, n72,
             n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
             n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
             n103, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
             n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
             n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
             n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
             n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
             n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
             n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
             n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
             n192, n193, n194, n195, n196, n197, n199, n200, n201, n202, n203,
             n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
             n215, n216, n217, n218, n220, n221, n222, n223, n224, n225, n226,
             n227, n228, n230, n231, n232, n233, n234, n235, n236, n237, n238,
             n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
             n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
             n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
             n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
             n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
             n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
             n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
             n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
             n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
             n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
             n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
             n360, n361, n362, n363, n364, n365, n366, n367, n368;
      assign N121 = b[0];
      assign N192 = a[0];
    
      LATCHX1 \co_reg[3]  ( .CLK(N270), .D(N274), .Q(co[3]) );
      LATCHX1 \co_reg[2]  ( .CLK(N270), .D(N273), .Q(co[2]) );
      LATCHX1 \co_reg[1]  ( .CLK(N270), .D(N272), .Q(co[1]) );
      LATCHX1 \co_reg[0]  ( .CLK(N270), .D(N271), .Q(co[0]) );
      OA22X1 U109 ( .IN1(n99), .IN2(n341), .IN3(n276), .IN4(n100), .Q(n81) );
      OA221X1 U110 ( .IN1(n300), .IN2(n101), .IN3(n55), .IN4(n305), .IN5(n102), 
            .Q(n99) );
      AND2X1 U111 ( .IN1(n96), .IN2(n103), .Q(n102) );
      NAND4X0 U112 ( .IN1(n79), .IN2(n105), .IN3(n106), .IN4(n107), .QN(out[2]) );
      OA221X1 U113 ( .IN1(n108), .IN2(n109), .IN3(n282), .IN4(n110), .IN5(n111), 
            .Q(n107) );
      OA221X1 U114 ( .IN1(n112), .IN2(n283), .IN3(n113), .IN4(n305), .IN5(n114), 
            .Q(n111) );
      OA22X1 U117 ( .IN1(n284), .IN2(n117), .IN3(n118), .IN4(n119), .Q(n108) );
      OA22X1 U118 ( .IN1(n122), .IN2(n271), .IN3(n348), .IN4(n100), .Q(n106) );
      OA221X1 U119 ( .IN1(n282), .IN2(n101), .IN3(n61), .IN4(n305), .IN5(n302), 
            .Q(n122) );
      NAND4X0 U121 ( .IN1(n79), .IN2(n125), .IN3(n126), .IN4(n127), .QN(out[1]) );
      OA221X1 U122 ( .IN1(n128), .IN2(n109), .IN3(n332), .IN4(n129), .IN5(n130), 
            .Q(n127) );
      OA221X1 U123 ( .IN1(n131), .IN2(n57), .IN3(n132), .IN4(n305), .IN5(n133), 
            .Q(n130) );
      OA22X1 U126 ( .IN1(n137), .IN2(n339), .IN3(n139), .IN4(n322), .Q(n128) );
      OA22X1 U127 ( .IN1(n143), .IN2(n248), .IN3(n301), .IN4(n100), .Q(n126) );
      OA221X1 U128 ( .IN1(n135), .IN2(n92), .IN3(n332), .IN4(n101), .IN5(n302), 
            .Q(n143) );
      AND2X1 U130 ( .IN1(n145), .IN2(n146), .Q(n79) );
      OA221X1 U132 ( .IN1(n318), .IN2(n302), .IN3(n311), .IN4(n100), .IN5(n151), 
            .Q(n150) );
      OA222X1 U133 ( .IN1(n152), .IN2(n267), .IN3(n94), .IN4(n153), .IN5(n300), 
            .IN6(n154), .Q(n151) );
      OA22X1 U134 ( .IN1(n352), .IN2(n146), .IN3(n103), .IN4(n156), .Q(n154) );
      XNOR2X1 U135 ( .IN1(bi), .IN2(n158), .Q(n153) );
      AOI22X1 U137 ( .IN1(n163), .IN2(n157), .IN3(n91), .IN4(n343), .QN(n100) );
      OA22X1 U138 ( .IN1(n166), .IN2(n63), .IN3(n320), .IN4(n167), .Q(n149) );
      XNOR2X1 U139 ( .IN1(cin), .IN2(n158), .Q(n167) );
      AND2X1 U140 ( .IN1(n98), .IN2(n305), .Q(n166) );
      AO21X1 U142 ( .IN1(n282), .IN2(n172), .IN3(n173), .Q(n170) );
      OA22X1 U143 ( .IN1(n174), .IN2(n175), .IN3(n331), .IN4(n240), .Q(n173) );
      OR2X1 U144 ( .IN1(n172), .IN2(n282), .Q(n169) );
      AO21X1 U145 ( .IN1(n349), .IN2(n315), .IN3(n180), .Q(n179) );
      OA222X1 U146 ( .IN1(n171), .IN2(n313), .IN3(n366), .IN4(n177), .IN5(n338), 
            .IN6(n178), .Q(n180) );
      AND2X1 U148 ( .IN1(n124), .IN2(n181), .Q(n171) );
      OA22X1 U151 ( .IN1(n366), .IN2(n182), .IN3(n181), .IN4(n335), .Q(n183) );
      AND4X1 U155 ( .IN1(n300), .IN2(sel[2]), .IN3(n157), .IN4(sel[1]), .Q(n188)
             );
      AO22X1 U159 ( .IN1(n319), .IN2(n250), .IN3(n191), .IN4(n303), .Q(N273) );
      AO22X1 U162 ( .IN1(n74), .IN2(n115), .IN3(n192), .IN4(n303), .Q(N272) );
      AO22X1 U163 ( .IN1(n331), .IN2(n306), .IN3(n136), .IN4(n134), .Q(n115) );
      AO222X1 U165 ( .IN1(n74), .IN2(n134), .IN3(n303), .IN4(n193), .IN5(n194), 
            .IN6(n73), .Q(N271) );
      AO221X1 U166 ( .IN1(n48), .IN2(n195), .IN3(n196), .IN4(n341), .IN5(n197), 
            .Q(n194) );
      AO222X1 U171 ( .IN1(n206), .IN2(n121), .IN3(n207), .IN4(n298), .IN5(n54), 
            .IN6(n255), .Q(n201) );
      XNOR2X1 U173 ( .IN1(n209), .IN2(n211), .Q(n206) );
      XOR2X1 U176 ( .IN1(n216), .IN2(n215), .Q(n213) );
      AO21X1 U184 ( .IN1(n211), .IN2(n338), .IN3(n221), .Q(n220) );
      OA22X1 U186 ( .IN1(n224), .IN2(n347), .IN3(n299), .IN4(n60), .Q(n222) );
      AO22X1 U187 ( .IN1(n225), .IN2(n357), .IN3(n332), .IN4(n357), .Q(n217) );
      AO222X1 U195 ( .IN1(n285), .IN2(n232), .IN3(n304), .IN4(n232), .IN5(n49), 
            .IN6(n233), .Q(n195) );
      XNOR2X1 U196 ( .IN1(n233), .IN2(n308), .Q(n232) );
      XNOR2X1 U200 ( .IN1(n270), .IN2(n341), .Q(n202) );
      AO22X1 U202 ( .IN1(n311), .IN2(n355), .IN3(cin), .IN4(n158), .Q(n134) );
      NAND2X1 U204 ( .IN1(n121), .IN2(n220), .QN(n257) );
      AND2X2 U205 ( .IN1(n317), .IN2(n315), .Q(n241) );
      XNOR2X2 U206 ( .IN1(n315), .IN2(n222), .Q(n221) );
      AND2X1 U207 ( .IN1(n368), .IN2(n140), .Q(n216) );
      DELLN1X2 U208 ( .INP(n155), .Z(n352) );
      NOR4X0 U209 ( .IN1(n161), .IN2(n162), .IN3(n271), .IN4(n342), .QN(n160) );
      NBUFFX2 U210 ( .INP(n171), .Z(n349) );
      XNOR2X1 U211 ( .IN1(n271), .IN2(n324), .Q(n283) );
      INVX0 U212 ( .INP(n314), .ZN(n315) );
      NAND3X1 U213 ( .IN1(n271), .IN2(n313), .IN3(n61), .QN(n97) );
      NBUFFX2 U214 ( .INP(n92), .Z(n305) );
      NBUFFX2 U215 ( .INP(n187), .Z(n285) );
      NBUFFX2 U216 ( .INP(n184), .Z(n304) );
      DELLN1X2 U217 ( .INP(n58), .Z(n284) );
      NAND3X1 U218 ( .IN1(n183), .IN2(n317), .IN3(n315), .QN(n277) );
      AND2X1 U219 ( .IN1(n329), .IN2(n69), .Q(n354) );
      XNOR2X1 U220 ( .IN1(n253), .IN2(n333), .Q(n231) );
      AND2X1 U221 ( .IN1(n267), .IN2(n254), .Q(n181) );
      NAND3X0 U222 ( .IN1(n246), .IN2(n293), .IN3(n294), .QN(n255) );
      NBUFFX2 U223 ( .INP(n120), .Z(n298) );
      AO221X1 U224 ( .IN1(n251), .IN2(a[3]), .IN3(n306), .IN4(n342), .IN5(n141), 
            .Q(n177) );
      NAND3X0 U225 ( .IN1(n363), .IN2(n328), .IN3(n135), .QN(n123) );
      NBUFFX2 U226 ( .INP(n330), .Z(n367) );
      NBUFFX2 U227 ( .INP(n142), .Z(n251) );
      XNOR2X1 U228 ( .IN1(n306), .IN2(n338), .Q(n136) );
      OA221X1 U229 ( .IN1(n356), .IN2(n109), .IN3(n318), .IN4(n101), .IN5(n159), 
            .Q(n152) );
      OR3X1 U230 ( .IN1(n316), .IN2(n55), .IN3(n92), .Q(n268) );
      AO22X1 U231 ( .IN1(n306), .IN2(n234), .IN3(n275), .IN4(n316), .Q(n233) );
      OR2X1 U232 ( .IN1(n103), .IN2(n277), .Q(n105) );
      NAND2X1 U233 ( .IN1(n300), .IN2(n189), .QN(n278) );
      AO22X1 U234 ( .IN1(n303), .IN2(n342), .IN3(n319), .IN4(n276), .Q(n189) );
      NAND3X0 U235 ( .IN1(n109), .IN2(n320), .IN3(n94), .QN(N270) );
      NAND3X0 U236 ( .IN1(n74), .IN2(n115), .IN3(n283), .QN(n114) );
      NAND2X0 U237 ( .IN1(n190), .IN2(n74), .QN(n279) );
      NAND3X1 U238 ( .IN1(n74), .IN2(n134), .IN3(n57), .QN(n133) );
      NBUFFX2 U239 ( .INP(n248), .Z(n363) );
      NBUFFX2 U240 ( .INP(n367), .Z(n368) );
      NAND4X0 U241 ( .IN1(sel[1]), .IN2(n311), .IN3(n91), .IN4(sel[2]), .QN(n237)
             );
      AND2X1 U242 ( .IN1(n124), .IN2(n182), .Q(n178) );
      AND2X1 U243 ( .IN1(n149), .IN2(n147), .Q(n238) );
      AND3X1 U244 ( .IN1(n81), .IN2(n80), .IN3(n79), .Q(n239) );
      OAI21X1 U245 ( .IN1(n362), .IN2(n366), .IN3(n177), .QN(n240) );
      NBUFFX2 U246 ( .INP(n164), .Z(n343) );
      NBUFFX2 U247 ( .INP(n361), .Z(n301) );
      INVX0 U248 ( .INP(n271), .ZN(n348) );
      AOI222X1 U249 ( .IN1(n206), .IN2(n121), .IN3(n207), .IN4(n298), .IN5(n54), 
            .IN6(n255), .QN(n242) );
      XNOR2X1 U250 ( .IN1(n209), .IN2(n119), .Q(n207) );
      NAND2X1 U251 ( .IN1(n141), .IN2(n213), .QN(n293) );
      XNOR2X1 U252 ( .IN1(n215), .IN2(n217), .Q(n212) );
      NAND2X0 U253 ( .IN1(n272), .IN2(n243), .QN(n261) );
      AND2X1 U254 ( .IN1(n273), .IN2(n276), .Q(n243) );
      AND3X1 U255 ( .IN1(n289), .IN2(n287), .IN3(n288), .Q(n244) );
      AND3X1 U256 ( .IN1(n289), .IN2(n288), .IN3(n287), .Q(n245) );
      NAND2X0 U257 ( .IN1(n266), .IN2(n365), .QN(n236) );
      XOR2X1 U258 ( .IN1(n325), .IN2(n321), .Q(n228) );
      DELLN1X2 U259 ( .INP(n292), .Z(n246) );
      NAND2X1 U260 ( .IN1(n141), .IN2(n228), .QN(n264) );
      NAND2X1 U261 ( .IN1(n212), .IN2(n142), .QN(n292) );
      INVX0 U262 ( .INP(n329), .ZN(n247) );
      INVX0 U263 ( .INP(a[1]), .ZN(n248) );
      AO221X1 U264 ( .IN1(n186), .IN2(n184), .IN3(n120), .IN4(n267), .IN5(n187), 
            .Q(n182) );
      XNOR2X1 U265 ( .IN1(a[2]), .IN2(n363), .Q(n223) );
      NAND2X0 U266 ( .IN1(n239), .IN2(n82), .QN(out[3]) );
      INVX0 U267 ( .INP(n90), .ZN(n249) );
      INVX0 U268 ( .INP(n249), .ZN(n250) );
      NAND2X0 U269 ( .IN1(n290), .IN2(n291), .QN(n90) );
      INVX0 U270 ( .INP(n350), .ZN(n252) );
      INVX0 U271 ( .INP(n252), .ZN(n253) );
      NAND2X0 U272 ( .IN1(n327), .IN2(n306), .QN(n294) );
      AND3X1 U273 ( .IN1(n184), .IN2(n185), .IN3(n364), .Q(n254) );
      NAND2X0 U274 ( .IN1(n241), .IN2(n183), .QN(n124) );
      NAND3X0 U275 ( .IN1(n150), .IN2(n148), .IN3(n238), .QN(out[0]) );
      NAND2X0 U276 ( .IN1(n245), .IN2(n256), .QN(n260) );
      NAND2X0 U277 ( .IN1(n273), .IN2(n272), .QN(n256) );
      NAND3X0 U278 ( .IN1(n257), .IN2(n258), .IN3(n259), .QN(n205) );
      NAND2X0 U279 ( .IN1(n298), .IN2(n221), .QN(n258) );
      NAND2X1 U280 ( .IN1(n54), .IN2(n59), .QN(n259) );
      NAND2X1 U281 ( .IN1(n199), .IN2(n318), .QN(n272) );
      XOR2X1 U282 ( .IN1(n338), .IN2(n205), .Q(n204) );
      XOR2X1 U283 ( .IN1(n307), .IN2(n354), .Q(n230) );
      XOR2X1 U284 ( .IN1(n155), .IN2(b[3]), .Q(n218) );
      OR2X1 U285 ( .IN1(n244), .IN2(n195), .Q(n262) );
      NAND3X0 U286 ( .IN1(n260), .IN2(n262), .IN3(n261), .QN(n197) );
      NAND2X0 U287 ( .IN1(n142), .IN2(n227), .QN(n263) );
      NAND2X0 U288 ( .IN1(n361), .IN2(n353), .QN(n265) );
      NAND3X0 U289 ( .IN1(n263), .IN2(n264), .IN3(n265), .QN(n210) );
      NAND2X1 U290 ( .IN1(n203), .IN2(n285), .QN(n287) );
      AO21X1 U291 ( .IN1(bi), .IN2(n236), .IN3(n174), .Q(n193) );
      INVX0 U292 ( .INP(n347), .ZN(n266) );
      INVX0 U293 ( .INP(n266), .ZN(n267) );
      AND3X1 U294 ( .IN1(n268), .IN2(n237), .IN3(n269), .Q(n86) );
      NAND2X0 U295 ( .IN1(n90), .IN2(n286), .QN(n269) );
      INVX0 U296 ( .INP(n56), .ZN(n270) );
      INVX0 U297 ( .INP(n270), .ZN(n271) );
      NAND2X0 U298 ( .IN1(n200), .IN2(n201), .QN(n273) );
      INVX0 U299 ( .INP(n298), .ZN(n274) );
      INVX0 U300 ( .INP(n274), .ZN(n275) );
      INVX0 U301 ( .INP(n50), .ZN(n276) );
      INVX0 U302 ( .INP(n93), .ZN(n74) );
      NAND2X1 U303 ( .IN1(n278), .IN2(n279), .QN(N274) );
      XNOR2X1 U304 ( .IN1(a[3]), .IN2(n299), .Q(n85) );
      OR2X1 U305 ( .IN1(n300), .IN2(n83), .Q(n280) );
      OR2X1 U306 ( .IN1(n84), .IN2(n85), .Q(n281) );
      AND3X1 U307 ( .IN1(n280), .IN2(n281), .IN3(n86), .Q(n82) );
      NBUFFX2 U308 ( .INP(n308), .Z(n282) );
      INVX0 U309 ( .INP(n307), .ZN(n308) );
      INVX0 U310 ( .INP(n283), .ZN(n116) );
      AND2X1 U311 ( .IN1(n74), .IN2(n85), .Q(n286) );
      NAND2X0 U312 ( .IN1(n304), .IN2(n204), .QN(n288) );
      NAND2X0 U313 ( .IN1(n49), .IN2(n205), .QN(n289) );
      NAND2X0 U314 ( .IN1(n348), .IN2(n308), .QN(n290) );
      NAND2X0 U315 ( .IN1(n115), .IN2(n116), .QN(n291) );
      OR2X1 U316 ( .IN1(n242), .IN2(n204), .Q(n203) );
      NAND3X0 U317 ( .IN1(n292), .IN2(n293), .IN3(n294), .QN(n208) );
      XOR2X1 U318 ( .IN1(n295), .IN2(n297), .Q(n227) );
      NAND2X0 U319 ( .IN1(n360), .IN2(n359), .QN(n295) );
      INVX0 U320 ( .INP(n225), .ZN(n296) );
      INVX0 U321 ( .INP(n296), .ZN(n297) );
      INVX0 U322 ( .INP(n136), .ZN(n57) );
      INVX0 U323 ( .INP(n123), .ZN(n61) );
      INVX0 U324 ( .INP(n97), .ZN(n55) );
      INVX0 U325 ( .INP(n202), .ZN(n49) );
      NBUFFX2 U326 ( .INP(n312), .Z(n317) );
      NOR2X0 U327 ( .IN1(n345), .IN2(n361), .QN(n142) );
      INVX0 U328 ( .INP(n109), .ZN(n73) );
      NAND2X1 U329 ( .IN1(n343), .IN2(n157), .QN(n98) );
      NAND2X1 U330 ( .IN1(n157), .IN2(n76), .QN(n146) );
      INVX0 U331 ( .INP(n145), .ZN(n72) );
      INVX0 U332 ( .INP(n135), .ZN(n63) );
      NBUFFX2 U333 ( .INP(n312), .Z(n316) );
      OR2X1 U334 ( .IN1(n103), .IN2(n309), .Q(n125) );
      NOR2X0 U335 ( .IN1(n72), .IN2(n188), .QN(n147) );
      NAND3X0 U336 ( .IN1(n324), .IN2(n312), .IN3(n337), .QN(n185) );
      INVX0 U337 ( .INP(n344), .ZN(n345) );
      INVX0 U338 ( .INP(n141), .ZN(n60) );
      AO22X1 U339 ( .IN1(n348), .IN2(n235), .IN3(n304), .IN4(n317), .Q(n196) );
      INVX0 U340 ( .INP(n161), .ZN(n76) );
      OA21X1 U341 ( .IN1(n135), .IN2(n338), .IN3(n123), .Q(n132) );
      INVX0 U342 ( .INP(n346), .ZN(n347) );
      NOR2X0 U343 ( .IN1(n75), .IN2(n160), .QN(n159) );
      OA21X1 U344 ( .IN1(n348), .IN2(n98), .IN3(n302), .Q(n110) );
      NOR2X0 U345 ( .IN1(n70), .IN2(n78), .QN(n157) );
      NAND2X0 U346 ( .IN1(n168), .IN2(n76), .QN(n145) );
      AND2X1 U347 ( .IN1(n343), .IN2(n168), .Q(n303) );
      AND2X1 U348 ( .IN1(n326), .IN2(n310), .Q(n327) );
      INVX0 U349 ( .INP(n253), .ZN(n351) );
      NOR2X0 U350 ( .IN1(n249), .IN2(n85), .QN(n190) );
      INVX0 U351 ( .INP(sel[0]), .ZN(n78) );
      OA21X1 U352 ( .IN1(n276), .IN2(n95), .IN3(n96), .Q(n83) );
      OA21X1 U353 ( .IN1(n92), .IN2(n97), .IN3(n98), .Q(n95) );
      NAND2X0 U354 ( .IN1(sel[2]), .IN2(n77), .QN(n161) );
      INVX0 U355 ( .INP(sel[3]), .ZN(n70) );
      NOR2X0 U356 ( .IN1(sel[3]), .IN2(sel[0]), .QN(n165) );
      INVX0 U357 ( .INP(sel[1]), .ZN(n77) );
      NOR2X0 U358 ( .IN1(sel[0]), .IN2(n70), .QN(n91) );
      NAND2X0 U359 ( .IN1(n163), .IN2(sel[3]), .QN(n101) );
      NAND2X0 U360 ( .IN1(n163), .IN2(n168), .QN(n103) );
      NAND2X0 U361 ( .IN1(n163), .IN2(n165), .QN(n109) );
      NOR2X0 U362 ( .IN1(n77), .IN2(sel[2]), .QN(n163) );
      NOR2X0 U363 ( .IN1(n50), .IN2(a[2]), .QN(n184) );
      NBUFFX2 U364 ( .INP(b[3]), .Z(n299) );
      NBUFFX2 U365 ( .INP(n299), .Z(n300) );
      INVX0 U366 ( .INP(n50), .ZN(n340) );
      INVX0 U367 ( .INP(a[3]), .ZN(n50) );
      INVX0 U368 ( .INP(n62), .ZN(n361) );
      INVX0 U369 ( .INP(n75), .ZN(n302) );
      INVX0 U370 ( .INP(n96), .ZN(n75) );
      NAND2X0 U371 ( .IN1(n165), .IN2(sel[2]), .QN(n96) );
      NOR2X0 U372 ( .IN1(n78), .IN2(sel[3]), .QN(n168) );
      NAND2X0 U373 ( .IN1(n168), .IN2(sel[2]), .QN(n92) );
      INVX0 U374 ( .INP(n248), .ZN(n306) );
      INVX0 U375 ( .INP(b[2]), .ZN(n307) );
      OA21X1 U376 ( .IN1(n320), .IN2(n134), .IN3(n94), .Q(n131) );
      NAND2X0 U377 ( .IN1(n343), .IN2(n168), .QN(n94) );
      AO221X1 U378 ( .IN1(n169), .IN2(n170), .IN3(n156), .IN4(n300), .IN5(n103), 
            .Q(n148) );
      DELLN1X2 U379 ( .INP(n144), .Z(n309) );
      INVX0 U380 ( .INP(n345), .ZN(n310) );
      INVX0 U381 ( .INP(n345), .ZN(n311) );
      OA21X1 U382 ( .IN1(n320), .IN2(n115), .IN3(n94), .Q(n112) );
      INVX0 U383 ( .INP(b[3]), .ZN(n312) );
      INVX0 U384 ( .INP(n323), .ZN(n313) );
      INVX0 U385 ( .INP(n323), .ZN(n324) );
      NOR2X0 U386 ( .IN1(n348), .IN2(n313), .QN(n191) );
      INVX0 U387 ( .INP(n313), .ZN(n314) );
      OA21X1 U388 ( .IN1(n61), .IN2(n315), .IN3(n97), .Q(n113) );
      INVX0 U389 ( .INP(n365), .ZN(n318) );
      NBUFFX4 U390 ( .INP(n350), .Z(n365) );
      INVX0 U391 ( .INP(n93), .ZN(n319) );
      INVX0 U392 ( .INP(n319), .ZN(n320) );
      NAND2X0 U393 ( .IN1(n165), .IN2(n164), .QN(n93) );
      INVX0 U394 ( .INP(n140), .ZN(n321) );
      INVX0 U395 ( .INP(n321), .ZN(n322) );
      INVX0 U396 ( .INP(n67), .ZN(n323) );
      INVX0 U397 ( .INP(b[2]), .ZN(n67) );
      AND2X1 U398 ( .IN1(n218), .IN2(n346), .Q(n214) );
      NAND2X0 U399 ( .IN1(n360), .IN2(n359), .QN(n325) );
      NAND2X0 U400 ( .IN1(n202), .IN2(n316), .QN(n235) );
      NAND2X0 U401 ( .IN1(n223), .IN2(n316), .QN(n234) );
      NAND2X0 U402 ( .IN1(n317), .IN2(n179), .QN(n362) );
      INVX0 U403 ( .INP(n196), .ZN(n48) );
      DELLN1X2 U404 ( .INP(n218), .Z(n326) );
      NOR2X0 U405 ( .IN1(n301), .IN2(n337), .QN(n192) );
      OA21X1 U406 ( .IN1(n320), .IN2(n90), .IN3(n94), .Q(n84) );
      OA21X1 U407 ( .IN1(n301), .IN2(n98), .IN3(n302), .Q(n129) );
      NAND2X0 U408 ( .IN1(n301), .IN2(n78), .QN(n162) );
      INVX0 U409 ( .INP(n247), .ZN(n328) );
      INVX0 U410 ( .INP(b[1]), .ZN(n329) );
      INVX0 U411 ( .INP(b[1]), .ZN(n330) );
      INVX0 U412 ( .INP(n328), .ZN(n331) );
      INVX0 U413 ( .INP(n367), .ZN(n332) );
      INVX0 U414 ( .INP(n330), .ZN(n333) );
      INVX0 U415 ( .INP(n367), .ZN(n334) );
      INVX0 U416 ( .INP(n334), .ZN(n335) );
      INVX0 U417 ( .INP(n328), .ZN(n336) );
      INVX0 U418 ( .INP(n336), .ZN(n337) );
      INVX0 U419 ( .INP(n336), .ZN(n338) );
      NAND2X0 U420 ( .IN1(n346), .IN2(n231), .QN(n339) );
      INVX0 U421 ( .INP(n340), .ZN(n341) );
      INVX0 U422 ( .INP(n340), .ZN(n342) );
      NOR2X0 U423 ( .IN1(sel[2]), .IN2(sel[1]), .QN(n164) );
      NAND2X0 U424 ( .IN1(n202), .IN2(n318), .QN(n200) );
      NOR2X0 U425 ( .IN1(n310), .IN2(n351), .QN(n135) );
      INVX0 U426 ( .INP(n64), .ZN(n344) );
      NAND2X0 U427 ( .IN1(n351), .IN2(n339), .QN(n140) );
      NAND2X0 U428 ( .IN1(n344), .IN2(n231), .QN(n138) );
      INVX0 U429 ( .INP(n64), .ZN(n346) );
      OA21X1 U430 ( .IN1(n366), .IN2(n362), .IN3(n177), .Q(n176) );
      INVX0 U431 ( .INP(N121), .ZN(n350) );
      INVX0 U432 ( .INP(n223), .ZN(n54) );
      INVX0 U433 ( .INP(n222), .ZN(n59) );
      DELLN1X2 U434 ( .INP(n69), .Z(n366) );
      XOR2X1 U435 ( .IN1(n214), .IN2(n324), .Q(n215) );
      OA21X1 U436 ( .IN1(n304), .IN2(n285), .IN3(n242), .Q(n199) );
      NAND2X0 U437 ( .IN1(n331), .IN2(n358), .QN(n360) );
      NAND2X1 U438 ( .IN1(n236), .IN2(n65), .QN(n158) );
      INVX0 U439 ( .INP(n358), .ZN(n353) );
      AND2X1 U440 ( .IN1(n230), .IN2(N192), .Q(n226) );
      NOR2X0 U441 ( .IN1(n275), .IN2(n121), .QN(n118) );
      INVX0 U442 ( .INP(n366), .ZN(n355) );
      INVX0 U443 ( .INP(n355), .ZN(n356) );
      INVX0 U444 ( .INP(a[2]), .ZN(n56) );
      NOR2X0 U445 ( .IN1(n56), .IN2(n361), .QN(n120) );
      NOR2X0 U446 ( .IN1(a[3]), .IN2(n56), .QN(n187) );
      NAND2X0 U447 ( .IN1(n67), .IN2(n354), .QN(n155) );
      NOR2X0 U448 ( .IN1(n356), .IN2(n54), .QN(n117) );
      INVX0 U449 ( .INP(n174), .ZN(n65) );
      NOR2X0 U450 ( .IN1(n176), .IN2(n368), .QN(n175) );
      NBUFFX4 U451 ( .INP(n226), .Z(n357) );
      NAND2X0 U452 ( .IN1(n335), .IN2(n353), .QN(n359) );
      INVX0 U453 ( .INP(n226), .ZN(n358) );
      NOR2X0 U454 ( .IN1(n138), .IN2(n365), .QN(n225) );
      NOR2X0 U455 ( .IN1(n365), .IN2(n344), .QN(n174) );
      NOR2X0 U456 ( .IN1(n356), .IN2(n301), .QN(n137) );
      INVX0 U457 ( .INP(N121), .ZN(n69) );
      INVX0 U458 ( .INP(N192), .ZN(n64) );
      NAND2X0 U459 ( .IN1(n316), .IN2(n179), .QN(n144) );
      NAND2X0 U460 ( .IN1(n318), .IN2(n58), .QN(n119) );
      XOR2X1 U461 ( .IN1(n334), .IN2(n208), .Q(n209) );
      DELLN1X2 U462 ( .INP(n62), .Z(n364) );
      INVX0 U463 ( .INP(a[1]), .ZN(n62) );
      NOR2X0 U464 ( .IN1(n62), .IN2(N192), .QN(n141) );
      NAND2X0 U465 ( .IN1(n178), .IN2(n144), .QN(n172) );
      NAND2X0 U466 ( .IN1(n349), .IN2(n144), .QN(n156) );
      NAND2X0 U467 ( .IN1(n351), .IN2(n210), .QN(n211) );
      INVX0 U468 ( .INP(n210), .ZN(n58) );
      NAND2X0 U469 ( .IN1(n73), .IN2(n256), .QN(n80) );
      NOR2X0 U470 ( .IN1(n141), .IN2(n251), .QN(n139) );
      NOR2X0 U471 ( .IN1(n364), .IN2(a[2]), .QN(n121) );
      OA21X1 U472 ( .IN1(n308), .IN2(n217), .IN3(n364), .Q(n224) );
      NAND2X0 U473 ( .IN1(n364), .IN2(n347), .QN(n186) );
    endmodule
    please help me i want to eliminate these warnings how can i.....................thanks in advance

    •   Alt28th April 2013, 08:55

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  2. #2
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    Re: how to eliminate the warnings in gate level simulation

    Error suppression switches are different in different simulators. If it is Questa, use "+nosdferror" with vsim command. eg: "vsim +nosdferror +sdf_verbose"



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    Re: how to eliminate the warnings in gate level simulation

    Quote Originally Posted by paulki View Post
    Error suppression switches are different in different simulators. If it is Questa, use "+nosdferror" with vsim command. eg: "vsim +nosdferror +sdf_verbose"
    hi paulki,
    i am using synopsys tool for gate level simulation
    so when i use the command vcs -debug_pp -sdf max:alu:alu.sdf stimuls +neg_tchk for removing the negative timing slacks in the code so what about the warnings



    •   Alt28th April 2013, 15:05

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  4. #4
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    Re: how to eliminate the warnings in gate level simulation

    +sdfverbose diplays only 10 warnings...there are after there is not any warnings in the log file....so we need to use +sdfverbose switch for VCS simulator...



    •   Alt29th April 2013, 04:37

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    Re: how to eliminate the warnings in gate level simulation

    can anyone please explain how to eliminate the IOPATH not found warning mentioned above. can i edit the sdf file. what is the warning about continuous assignment of a[0] in the warning



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    Re: how to eliminate the warnings in gate level simulation

    We don't need to edit SDF file as it is not the solution..because these violation may help if you get simulation mismatch....
    you can use : disable_warning ("timing"(instance_name,..]) this switch is for vcs....
    If you read VCS user guide, you will find good options/switches/commands.



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    Re: how to eliminate the warnings in gate level simulation

    Quote Originally Posted by maulin sheth View Post
    We don't need to edit SDF file as it is not the solution..because these violation may help if you get simulation mismatch....
    you can use : disable_warning ("timing"(instance_name,..]) this switch is for vcs....
    If you read VCS user guide, you will find good options/switches/commands.
    iam getting port mismatch problems and warnings how can i eliminate them



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    Re: how to eliminate the warnings in gate level simulation

    Quote Originally Posted by maheshkumar.g View Post
    iam getting port mismatch problems and warnings how can i eliminate them
    first read the documents.. i have already told you that use the disable_warning command..you jus need to see it for how to use it...just the read the user guide properly......

    For mismatch, means circuit is not working properly....so you need to debug it.....why are ou worry about warning..as you got the mismatch....so first thing to clear the mismatch...as patterns are failing...



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    Re: how to eliminate the warnings in gate level simulation

    Quote Originally Posted by maulin sheth View Post
    first read the documents.. i have already told you that use the disable_warning command..you jus need to see it for how to use it...just the read the user guide properly......

    For mismatch, means circuit is not working properly....so you need to debug it.....why are ou worry about warning..as you got the mismatch....so first thing to clear the mismatch...as patterns are failing...
    thank you maulin i am working on it



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