Divide by 11 Frequency divider

I am trying to design a divide by 66 freq. divider and I am can not find a topology for building this block, help is really appreciated.

Thank you

In case you are using CMOS IC's:

If you cascade two 4017 decade counters, you can tap the '6' outputs and feed them to the inputs of an AND gate. It will produce a pulse every 66 counts. Wire the signal so it resets the 4017's.

Or if you are using 7400 series (some of the following might have a counterpart in CMOS):

7493 '4-bit binary counter' can divide by 11 with the addition of an AND gate (7408).

7492 'divide-by-12 counter' can be made to divide by various odd numbers. Seems there should be a way to divide by 11.

74193 '4-bit up/down counter' can either (a) count up to N and recycle, or (b) count down from N after loading a 4-bit pattern when pin 11 is brought low.

74154, '4 line to 16-line decoder'. Has 16 output wires. Not sure if this can do what you want.

Actually I am designing an integrated circuit, and it is working on 1.6GHz so it i need a speed efficient design. Sorry for not mentioning this in the beginning.

Thank you

If you cascade 6 flip flops, that divides by 64. Additionally tap the flip flop that contains bit 2. Feed those lines to your AND gate.

When those two lines both go high, you are dividing by 66.

Reset those two flip flops.

(I may be off by one. It's either 0 to 65, or 1 to 66.)

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I guess you have looked into the high speed families of the 7400 TTL IC's. (HC, etc.)