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use of (); in verilog and system verilog

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sunidrak

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hi
Can any plz tell what does this means and what is the difference?


class base;
task print();
.......
endtask
endclass

and

class base;
task print;
.......
endtask
endclass[/FONT


i.e use of (); in coding


Regards
Sunil
 

The Verilog language was not written for programmers. It was written for people who were design engineers who didn't like writing code (or just plain lazy about it). They would take any shortcut they could get, even if it was the result of a bug in their simulator.

In Verilog and SystemVerilog declarations, you can omit an empty set of parenthesis () if you want to; there is not difference between using them or not.

However, when you reference that declaration, the empty parenthesis is sometimes required by the syntax. For example, when you declare a module, if there are not ports, the parenthesis are optional, but when you instantiate the module, the parenthesis are required regardless of whether there are ports or not.

Code: 
module bottom;   // bottom(); is optional
endmodule
module top;

bottom b1(); // parenthesis are required.

endmodule

My recommendation is to always use the ()'s when referencing a module or calling a task/function even when they are optional. This shows that you were aware that there were either no argument/ports or wanted the all the defaults.

Code: 
assign X = Y + Z(); // Z is a function call. (Verilog required functions to have at least one argument and there were no defaults)

myModule #() inst1(); // This tells me myModule is a parametrized module, but the default values are OK for this instance
 

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