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Is the deep nwell process allowed in TSMC65 technology?

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Alex Liao

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I placed a nch (nmos) in a pw and pw is on a deep newll which is within the nwell on a p-substrate. Please refer the attachment for reference of the placement.

I cannot pass the LVS and have information like this:
Error Message:
Nothing in Layout; corresponding cells could not be identified;Nothing in Layout.
D-nwell.png
 

Depending on your PDK, isolated nmosfets probably need additional recognition layers to be recognized as such by the extraction tool.
Read your PDK docu!

If TSMC supports the deep nwell option in 65nm tech you should ask MOSIS or TSMC themselves.
 
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