shady_Sayed
Newbie level 1
Greetings,
I have been working lately on a small project on designing a folded cascade fully differential OTA with output swing of 4Vpp using a supply of 2.7Volt using MOSFET, which means that each output node must swing freely in a range of 2volts without making any transistor get out of the saturation region. Leaving only 0.7volt to be distributed as overdrive ( |Vgs-Vth| ) on the load transistors. All of this is fine the problem is that in order to get a common mode output of half the supply (1.35V) then 0.35 of the 0.7 will be given to the NMOS load (lower half of the circuit) and the other 0.35 will be given to the PMOS load (upper half of the circuit). Which means that the output can get as low as 0.35 volt (which inhibits me from using NMOS differential difference amplifier (DDA) to sense the output common mode since one of the two transistors will enter the off region when its gate is at 0.6 V. ) and also the output can get as high as 2.7-0.35 (which inhibits me from using PMOS DDA).
The technology parameters are Vtn=0.6 Vtp=0.75
My question is
How can I sense the common mode output level correctly, without making the high swing of the differential signal affect the CM measurement?
Note: if I used an Averaging Caps or Resistors the output impedance drops significantly, so I cant use this technique.
I have been working lately on a small project on designing a folded cascade fully differential OTA with output swing of 4Vpp using a supply of 2.7Volt using MOSFET, which means that each output node must swing freely in a range of 2volts without making any transistor get out of the saturation region. Leaving only 0.7volt to be distributed as overdrive ( |Vgs-Vth| ) on the load transistors. All of this is fine the problem is that in order to get a common mode output of half the supply (1.35V) then 0.35 of the 0.7 will be given to the NMOS load (lower half of the circuit) and the other 0.35 will be given to the PMOS load (upper half of the circuit). Which means that the output can get as low as 0.35 volt (which inhibits me from using NMOS differential difference amplifier (DDA) to sense the output common mode since one of the two transistors will enter the off region when its gate is at 0.6 V. ) and also the output can get as high as 2.7-0.35 (which inhibits me from using PMOS DDA).
The technology parameters are Vtn=0.6 Vtp=0.75
My question is
How can I sense the common mode output level correctly, without making the high swing of the differential signal affect the CM measurement?
Note: if I used an Averaging Caps or Resistors the output impedance drops significantly, so I cant use this technique.
