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Using "initial" for my FPGA programming

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daisordan

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I am using CycloneII and trying to do a simply communication using RS232 with my PC.
My simulation in modelsim is fine but it came wrong after it loaded into the FPGA. I use the oscilloscope to check the pin and the FPGA didnt run the initial value part. I did somethings simply like:
Code: 
initial
begin
a<=0;
count<=0;
b<=1;
end

Is that because I cannot use "initial" for "real world" FPGA design? As I know RS232 doesnt included reset pin so I can only start with some initial value and use a counter to reset the value after each complete process?
 

Your assumption is wrong

Initial blocks are synthesized as register power-on reset, except for some special cases where it's ignored by the synthesis tool. You'll be warned about it.

I don't understand the connection of RS232 and reset pin. A FPGA can have a reset pin, and it's generally reasonable to implement it. A RS232 module should be able to rest itself to idle state when no communication is going on. In so far I don't believe that the problem is actually related to reset or initial state, rather to an incomplete design.

We'll need to see more code than an initial block to discuss the real problem.
 
Last edited:

FvM said:
Initial blocks are synthesized as register power-on reset, except for some special cases where it's ignored by the synthesis tool.
Click to expand...

And on that subject, it can be quite educational to look at the synthesized result. For example in ISE check out "View RTL Schematic" and "View Technology Schematic" to see what I mean. This can be useful when you want to verify you are getting what you intend. And for this particular case you would see how your initial statements affect the power on reset of the flip flops in question.
 

Thanks for the reply

In my case, I give some value to the FPGA when there is no input from the PC. For example, the FPGA will stay at idle state when there is no input (in=0) detected. Therefore i write my initial state like :
Code: 
parameter idle=1'b1;
parameter startup=1'b0;
initial
begin
state<=idle;
count<=4'b0000;
end

always@(posedge clk)
    case(state)
      idle:                 
        begin
        if(in==0 & count==0)
          state<=startup;
        end
      start:                
        begin
        if(in==1 & count>12)
          state<=idle;
        else
          state<=startup;
        end
      default:state<=idle;
    endcase

The problem is everythings is working good in my modelsim simulation. Thats doing what i want. But when I use the oscilloscope to check the signal, the "state" signal is staying at "0" when I power on my FPGA, but not "1".

In RS232, the "in" will be "1" if there is no input. When there is an input, the "in" will become "0" (start bit).

Hope I make my question clear now.
 

There's a couple of things, but lets start with this one... You do a "state<=startup", but your case statement only handles "idle", "start" and "default". So maybe you have a "start" vs "startup" typo in there?

Also, if it still doesn't work after fixing that, please post the full code + testbench you are using, because I am somewhat surprised that the sim is working. The code as you posted it I can understand why it stays in state 0. Anyways, fix typo first and see if that fixes it.
 

Another point is that if Altera Quartus recognizes a state machine, it will use default one state hot coding for the state variable, despite of the coding used in the HDL text. The state machine viewer tells you the actually used coding.
 

Re: Using &quot;initial&quot; for my FPGA programming

mrflibble said:
There's a couple of things, but lets start with this one... You do a "state<=startup", but your case statement only handles "idle", "start" and "default". So maybe you have a "start" vs "startup" typo in there?

Also, if it still doesn't work after fixing that, please post the full code + testbench you are using, because I am somewhat surprised that the sim is working. The code as you posted it I can understand why it stays in state 0. Anyways, fix typo first and see if that fixes it.
Click to expand...

Thanks,
Sorry I type that wrongly, they should be startup but not start. After I fix it, it still doesnt work. I have try to change the "state" to "idle" or startup" in the initial block. The oscilloscope gave me the same things, which keep stay at 0. Also I have try to add another state like "processing" in the initial block. Whatever I change the value or state in the initial block, oscilloscope keep showing me the same result. Do you have any suggestion wt i can try to do?>

- - - Updated - - -

FvM said:
Another point is that if Altera Quartus recognizes a state machine, it will use default one state hot coding for the state variable, despite of the coding used in the HDL text. The state machine viewer tells you the actually used coding.
Click to expand...
Thanks

Do u mean the problem come from default:state<=idle;? because the state is not able to go to "start" so it stay at the default part?

After I fix my code, the problem is still here :(
 

The problem is that you didn't report actual results except for the state variable not having the expected initial value. As explained, this point doesn't mean much. The state variable would still be initilized to idle, but the state doesn't show as expected.

You might have observed other problems, but you didn't report it yet.
 

Re: Using &quot;initial&quot; for my FPGA programming

daisordan said:
Sorry I type that wrongly, they should be startup but not start. After I fix it, it still doesnt work.

...

Do you have any suggestion wt i can try to do?>
Click to expand...

Yes I have.

mrflibble said:
Also, if it still doesn't work after fixing that, please post the full code + testbench you are using ...
Click to expand...

I suggest you post code + testbench. Because as pointed out:

FvM said:
The problem is that you didn't report actual results except for the state variable not having the expected initial value. As explained, this point doesn't mean much. The state variable would still be initilized to idle, but the state doesn't show as expected.
Click to expand...

... all you have basically said is "it doesn't do what I want", and then give incomplete information. It's kinda tricky to help in that situation. So full code + testbench please. Otherwise it's going to be an endless guessing game, which sometimes is fun but not today. :p
 

maybe you want to try add "reset" signal in your always. something like
Code Verilog - [expand]
1
2
3
4
5

always(clk,rst)
  if(rst)
    state <= idle;
  else if(posedge(clk))
   case:
 

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