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designing a moore fsm for even no of zeros and odd no of ones

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sireesha92

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How to design a Moore FSM which detects even number of zeros and odd number of ones.? The output of the FSM has to be one for one clock pulse if the specified condition is met else the output has to remain zero.
 

You can do this with 4 states: even #0's/even #1's, even #0's/odd #1's, odd #0's/even #1's, and odd #0's/odd #1's. From there you can figure out the state transitions and outputs.
 
Thank you for the information.. Can please draw the moore state diagram for this...??

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Is this state diagram correct..?
moore.png
 

HI there ,can u plz provide me with a verilog code (behavioural model) for the same.
 

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