hsnhsyn1
Junior Member level 1
hello, i designed an edge detector in verilog. it's RTL seems correct, but in simulation the output pulse is delayed. The examples on the internet, the pulse starts exactly with the rising edge of the clock signal. i used no delay in simulation.
capture from the simulation
and the code
capture from the simulation
and the code
Code:
module re_detector(Clk, sign_in, Sync_clk);
// input ports
input Clk, sign_in;
// output ports
output wire Sync_clk;
reg Q;
wire sign_in;
always@(posedge Clk)begin
Q <= sign_in;
end
assign Sync_clk = sign_in & (~Q);
endmodule