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Syntheis report in Xilinx

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samiksha

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I'm designing a structure in VHDL with clock. the design is getting simulated and giving me the correct output but when i synthesise that code, i get the following information regarding delay.

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
And also the area result does not show any LUT utilization?
Can anyone let me know the problem in the design?
 

This usually happens when all of your logic is synthesised away, for various resons, but the two usual culprits are
1. you have no outputs
2. a clock is stuck at 1 or 0, or a reset is stuck at '1', or an enable stuck at '0'.
 

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