Clock tree dynamic power

Hi

I needed to know how much does clock physical distribution affect the clock tree power .
Is it too much dependent on number of distribution stages of clock or just the loading on final distribution stage
How can I optimize the clock tree dynamic power just by changing physical distribution ?

It depends on clock distribution. It is typically 50% of dynamic power of your design.

Depends also on the technology that you are using.

Actually there are bunch of things which determine the clock tree power
a) Choice of cells high Vt or low Vt : Low Vt will consume higher power. For high frequency designs low Vt cells should be used for clock tree.
b) buffers or inverters : this has been a key question across many generation. from industry experience people use buffers for their design, but for high performance you should use inverter.
c) clock tree should be symmetric ...to do so keep the transition times, clock buffer/inverter the same with the same load.
d) clock shielding should be done probably dynamic shielding.

Global clock tree should be preplanned with the number of buffers/inverters you need to use. Local can be a bit random ( read CTS tool for doing the clock tree). If possible clk tree should be analysed using spice tools as well.

prassingh said:

Hi

I needed to know how much does clock physical distribution affect the clock tree power .
Is it too much dependent on number of distribution stages of clock or just the loading on final distribution stage
How can I optimize the clock tree dynamic power just by changing physical distribution ?

Click to expand...

artmalik said:

Actually there are bunch of things which determine the clock tree power
a) Low Vt will consume higher power. For high frequency designs low Vt cells should be used for clock tree.

Global clock tree should be preplanned with the number of buffers/inverters you need to use. Local can be a bit random ( read CTS tool for doing the clock tree). If possible clk tree should be analysed using spice tools as well.

Click to expand...

Why is that so?.

If you have any article on the same , it would be really helpful!!

Generally the leakage power goes high when you reduce Vt of a CMOS transistor . So if you are using low Vt cells on clock paths then your power will go up. But the advantage is low vt cells are faster . You would see good transitions on clock path with low vt cells . So you need to make a tradeoff as per your requirements