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best approach for multi VT cell usage for leakage power optimization

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alokem

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What should be the best multi VT optimization approach for leakage power
optimization targating the usage of maximum no. of high VT cells without degrading
timing ?

1) Low VT -> Std VT -> High VT
2) High VT -> Std VT -> Low VT
or anyother approach ?
 

Close timing which high vt cells and see where ever timing critical try to use less vt cells.
 

Yes. Using only low Vt will require buffers insertion and other compensations methods for timing closure.
 

HVT -> High Delay and Less Leakage
LVT -> Less Delay and High Leakage

The approach is, use only HVT from Synthesis to Route.

Allow LVT cells only after Post-Route Optimization, this will have less overall leakage.

Again, it depends on the design & varies from design to design.
 

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