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cadence layout warning: gate used as conductor

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yuxiaojian01

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Hi,everyone,
There is a warning "gate used as conductor" after DRC when I use cadence to create layout. The layout is shown in the figure. What's the meaning of the warning? Does that mean I can't connect two transistor's gate using poly?
Thanks. 未命名.jpg
 

yuxiaojian01 said:
Does that mean I can't connect two transistor's gate using poly?
Click to expand...

That's not a problem. But the warning suggests there's a current flowing through the 2 gate's poly lines (not observable from your layout snippet), which could result in changing gate voltage over the transistor's width - on its part resulting in inaccurate drain current calculation by later simulation.

DC current flow (apart from leakage) is not allowed for gate connections.
 
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