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How to get a good verilog gate_level netlist for DC?

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seanwu

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bug in DC

I have use DC V2004.06 to synthesis a simple verilog design and output the compile results in both db and verilog format. When I read the result file into DC and run check_design command, the bug appears: in db file no error and warning, in verilog file a few of cells has floating input pins.
How to get a good verilog gate_level netlist ?
 

bug in DC

It's a design risk that cells in design have float input pin.
you can check it or use another DC version.
Thanks
 

Re: bug in DC

I hear this version is B-version for test user .
or maybe you can check your code to see whether float gate can get right result
 

bug in DC

maybe it's really true that the newest one is not always the best ! As for me ,i use a very old version,i think it also not a good choice,but it is decided by the enviroment,so it is very pity !
 

Re: bug in DC

seanwu said:
I have use DC V2004.06 to synthesis a simple verilog design and output the compile results in both db and verilog format. When I read the result file into DC and run check_design command, the bug appears: in db file no error and warning, in verilog file a few of cells has floating input pins.
How to get a good verilog gate_level netlist ?
Click to expand...

Yes, the 2004-06 have some bugs. I also meet them.
And frequently fital error or out of memory.
But the bug you said is random, rewrite or retry may resolved it.
 

Re: bug in DC

Check your DC setup files carefully.
Then you can conclude what causes the problem.
I have use the new version DC 2004.06. But i have not encounted this problem.
 

Re: bug in DC

It's really? too horible.
I am now using 03.06. it's ok only when use change_name at TCL mode, bug will come out
 

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