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Timing Doubts!! Need Claricfication

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Prashanthanilm

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Hi all,

These are few questions:
1. Why there is Negative Hold time?
2.Whether it is good or bad to have negative hold time? Why?
3.Whether Set up + Hold Time can be 0 or >0 or <0?
4.For a D-FF, we have Set up and Hold wrt to Clock. But what is the criteria of a clock signal? How much min width a clock signal be?

Thank you,
Prashanth
 

1): setup / hold are calculated at the point which the clock and data reach at the DFF clock pin and data pins. And there will be delays in the DFF cell itself on both clock and data pathes. For negative hold time, you can image there is a large delay within the DFF cell on the data path (so, this need larger setup time requirement).
2): negative setup time cell are good for path with short delay (no need to add buffers to fix hold violation), while bad for path with longer delay. So, the cell library must have both positive and negative hold time DFF cells.
3): setup time + hold time must be > 0.
4): Of case there will be min_pulse_width requirement on clock pin of the DFF cells. You can see the cell library (*.lib) by yourself.
 

asic_service said:
For negative hold time, you can image there is a large delay within the DFF cell on the data path (so, this need larger setup time requirement).
2): negative setup time
3): setup time + hold time must be > 0.
4): Of case there will be min_pulse_width requirement on clock pin of the DFF cells. You can see the cell library (*.lib) by yourself.
Click to expand...

Confused:
1. Please Elaborate the statement. I am feeling difficulty to understand.
2.Negative Set up time??? If it hold time- How come it is good for shorter path and good for longer path. What do you mean by path, Which path??
3.What happens if we have the sum < or =0
4.Can I calculate manually? It has some equation I suppose.

Thank for the post above. Hope you clear these doubts too.
 

Hi,

1. Negative hold time means that the hold value is very small and in real cases will be assumed to be zero.
2. The negative hold time should be good as if there are hold delay in final chip it will becoma a garbage. And having negative hold may have sifde effects like lowering freq of operation by increasing setup.
3.>0
4. Minimum clk sgl width > setup time and this inturn depends on library u use.
 

sakthikumaran87 said:
Hi,
2. The negative hold time should be good as if there are hold delay in final chip it will becoma a garbage. And having negative hold may have sifde effects like lowering freq of operation by increasing setup.
3.>0
4. Minimum clk sgl width > setup time and this inturn depends on library u use.
Click to expand...

Thanks Sakthikumar.

Clarifications:
1.So, Even Hold time can be negative also right.?(You didnt mention it to be negative)
2.having negative hold may have sifde effects like lowering freq of operation by increasing setup.

Whether Set up is dependant on Hold time?.Why? ; If not, how set up is increased as you said?
3.So, The sum is always positive huh?.. Any typical chances that Set up+Hold time can be negative???
4.Can you please upload some article regarding this (Clock signal > Set up time).

Doubt:
1.Whether Set up time can be negative??
 

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